Zhenzhong Duan 860bb8b925 hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class ... RISCVIOMMUPciClass and RISCVIOMMUSysClass are defined with missed parent class, class_init on them may corrupt their parent class fields. It's lucky that parent_realize and parent_phases are not initialized or used until now, so just remove the definitions. They can be added back when really necessary. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250606092406.229833-6-zhenzhong.duan@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		2025-06-10 12:59:09 +02:00
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boot.h	hw/riscv: Add the checking if DTB overlaps to kernel or initrd	2024-12-20 11:22:47 +10:00
boot_opensbi.h	target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI	2024-10-30 11:22:07 +10:00
iommu.h	hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class	2025-06-10 12:59:09 +02:00
microchip_pfsoc.h	hw/riscv: Configurable MPFS CLINT timebase freq	2025-05-19 13:30:24 +10:00
numa.h	include: Rename sysemu/ -> system/	2024-12-20 17:44:56 +01:00
opentitan.h	hw/riscv/opentitan: Correct OpenTitanState parent type/size	2023-06-13 17:19:42 +10:00
riscv_hart.h	target/riscv: Handle Smrnmi interrupt and exception	2025-01-19 09:44:34 +10:00
shakti_c.h	hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0	2023-01-06 10:42:55 +10:00
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e.h	hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.	2023-07-10 22:29:15 +10:00
sifive_u.h	hw/riscv: Move the dtb load bits outside of create_fdt()	2023-03-01 17:19:14 -08:00
spike.h	hw/riscv/spike: use 'fdt' from MachineState	2023-01-20 10:14:13 +10:00
virt.h	hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structure	2025-05-19 11:07:13 +10:00