mirror of
https://github.com/Motorhead1991/qemu.git
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08572022e5
* hw/arm/sbsa-ref: set 'slots' property of xhci
* linux-user: Remove pointless NULL check in clock_adjtime handling
* ptw: Fix S1_ptw_translate() debug path
* ptw: Account for FEAT_RME when applying {N}SW, SA bits
* accel/tcg: Zero-pad PC in TCG CPU exec trace lines
* hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
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Merge tag 'pull-target-arm-20230717' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm/sbsa-ref: set 'slots' property of xhci
* linux-user: Remove pointless NULL check in clock_adjtime handling
* ptw: Fix S1_ptw_translate() debug path
* ptw: Account for FEAT_RME when applying {N}SW, SA bits
* accel/tcg: Zero-pad PC in TCG CPU exec trace lines
* hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
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# gpg: Signature made Mon 17 Jul 2023 01:47:01 PM BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
* tag 'pull-target-arm-20230717' of https://git.linaro.org/people/pmaydell/qemu-arm:
hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
accel/tcg: Zero-pad PC in TCG CPU exec trace lines
target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits
target/arm: Fix S1_ptw_translate() debug path
target/arm/ptw.c: Add comments to S1Translate struct fields
linux-user: Remove pointless NULL check in clock_adjtime handling
hw/arm/sbsa-ref: set 'slots' property of xhci
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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