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Taylor Simpson 523e45ac5b Hexagon: lldb read/write predicate registers p0/p1/p2/p3 
hexagon-core.xml only exposes register p3_0 which is an alias that
aggregates the predicate registers.  It is more convenient for users
to interact directly with the predicate registers.

Tested with lldb downloaded from this location
https://github.com/llvm/llvm-project/releases/download/llvmorg-18.1.4/clang+llvm-18.1.4-x86_64-linux-gnu-ubuntu-18.04.tar.xz

BEFORE:
(lldb) reg read p3_0
    p3_0 = 0x00000000
(lldb) reg read p0
error: Invalid register name 'p0'.
(lldb) reg write p1 0xf
error: Register not found for 'p1'.

AFTER:
(lldb) reg read p3_0
    p3_0 = 0x00000000
(lldb) reg read p0
      p0 = 0x00
(lldb) reg read -s 1
Predicate Registers:
        p0 = 0x00
        p1 = 0x00
        p2 = 0x00
        p3 = 0x00

(lldb) reg write p1 0xf
(lldb) reg read p3_0
    p3_0 = 0x00000f00
(lldb) reg write p3_0 0xff00ff00
(lldb) reg read -s 1
Predicate Registers:
        p0 = 0x00
        p1 = 0xff
        p2 = 0x00
        p3 = 0xff

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Message-Id: <20240613182209.140082-1-ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>
2024-08-07 20:34:41 -07:00
..
alpha target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
arm hvf: arm: Fix hvf_sysreg_read_cp() call 2024-08-03 07:24:12 +10:00
avr target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
cris target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
hexagon Hexagon: lldb read/write predicate registers p0/p1/p2/p3 2024-08-07 20:34:41 -07:00
hppa target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
i386 target/i386: Fix VSIB decode 2024-08-05 14:14:47 +02:00
loongarch target/loongarch: Fix helper_lddir() a CID INTEGER_OVERFLOW issue 2024-07-24 16:52:18 +08:00
m68k target/m68k: avoid shift into sign bit in dump_address_map() 2024-07-29 16:58:58 +01:00
microblaze target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
mips target/mips: Restrict semihosting to TCG 2024-07-22 09:38:10 +01:00
openrisc target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
ppc target/ppc: Remove includes from mmu-book3s-v3.h 2024-07-26 09:51:34 +10:00
riscv target/riscv: Add asserts for out-of-bound access 2024-08-06 14:20:16 +10:00
rx target/rx: Use target_ulong for address in LI 2024-07-28 14:13:05 +10:00
s390x target/s390x: move @deprecated-props to CpuModelExpansion Info 2024-07-29 21:47:16 +02:00
sh4 target/sh4: Avoid shift into sign bit in update_itlb_use() 2024-07-29 17:00:20 +01:00
sparc sparc/ldst_helper: make range overlap check more readable 2024-07-23 20:30:36 +02:00
tricore target/tricore: Use unsigned types for bitops in helper_eq_b() 2024-07-29 16:57:27 +01:00
xtensa target/xtensa: Correct assert condition in handle_interrupt() 2024-08-01 10:59:01 +01:00
Kconfig meson: make target endianneess available to Kconfig 2024-05-03 15:47:47 +02:00
meson.build exec: Expose 'target_page.h' API to user emulation 2024-04-26 15:28:11 +02:00