mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-12-26 17:38:37 -07:00
51fd06e0ee
A GICv2 has both GICC_APR<n> and GICC_NSAPR<n> registers, with the latter holding the active priority bits for Group 1 interrupts (usually Nonsecure interrupts), and the Nonsecure view of the GICC_APR<n> is the second half of the GICC_NSAPR<n> registers. Turn our half-hearted implementation of APR<n> into a proper implementation of both APR<n> and NSAPR<n>: * Add the underlying state for NSAPR<n> * Make sure APR<n> aren't visible for pre-GICv2 * Implement reading of NSAPR<n> * Make non-secure reads of APR<n> behave correctly * Implement writing to APR<n> and NSAPR<n> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1438089748-5528-4-git-send-email-peter.maydell@linaro.org |
||
|---|---|---|
| .. | ||
| block | ||
| crypto | ||
| disas | ||
| exec | ||
| fpu | ||
| hw | ||
| libdecnumber | ||
| migration | ||
| monitor | ||
| net | ||
| qapi | ||
| qemu | ||
| qom | ||
| standard-headers | ||
| sysemu | ||
| ui | ||
| config.h | ||
| elf.h | ||
| glib-compat.h | ||
| qemu-common.h | ||
| qemu-io.h | ||
| qjson.h | ||
| trace-tcg.h | ||
| trace.h | ||