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The HPM (Hardware Performance Monitor) support consists of almost 7 hundred lines that would be put on top of the base riscv-iommu emulation. To avoid clogging riscv-iommu.c, add a separated riscv-iommu-hpm file that will contain HPM specific code. We'll start by adding riscv_iommu_hpmcycle_read(), a helper that will be called during the riscv_iommu_mmio_read() callback. This change will have no effect on the existing emulation since we're not declaring HPM feature support. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
54 lines
1.9 KiB
C
54 lines
1.9 KiB
C
/*
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* RISC-V IOMMU - Hardware Performance Monitor (HPM) helpers
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*
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* Copyright (C) 2022-2023 Rivos Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/timer.h"
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#include "cpu_bits.h"
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#include "riscv-iommu-hpm.h"
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#include "riscv-iommu.h"
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#include "riscv-iommu-bits.h"
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#include "trace.h"
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/* For now we assume IOMMU HPM frequency to be 1GHz so 1-cycle is of 1-ns. */
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static inline uint64_t get_cycles(void)
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{
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return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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}
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uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s)
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{
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const uint64_t cycle = riscv_iommu_reg_get64(
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s, RISCV_IOMMU_REG_IOHPMCYCLES);
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const uint32_t inhibit = riscv_iommu_reg_get32(
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s, RISCV_IOMMU_REG_IOCOUNTINH);
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const uint64_t ctr_prev = s->hpmcycle_prev;
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const uint64_t ctr_val = s->hpmcycle_val;
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if (get_field(inhibit, RISCV_IOMMU_IOCOUNTINH_CY)) {
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/*
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* Counter should not increment if inhibit bit is set. We can't really
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* stop the QEMU_CLOCK_VIRTUAL, so we just return the last updated
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* counter value to indicate that counter was not incremented.
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*/
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return (ctr_val & RISCV_IOMMU_IOHPMCYCLES_COUNTER) |
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(cycle & RISCV_IOMMU_IOHPMCYCLES_OVF);
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}
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return (ctr_val + get_cycles() - ctr_prev) |
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(cycle & RISCV_IOMMU_IOHPMCYCLES_OVF);
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}
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