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qemu/target/riscv/insn_trans
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Rob Bradford 4f75d81225 target/riscv: Check 'A' and split extensions for atomic instructions 
Following the pattern for 'M' and Zmmul check if either the 'A'
extension is enabled or the appropriate split extension for the
instruction.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240123111030.15074-3-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-09 20:43:14 +10:00
..
trans_privileged.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rva.c.inc target/riscv: Check 'A' and split extensions for atomic instructions 2024-02-09 20:43:14 +10:00
trans_rvb.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvbf16.c.inc target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb 2024-02-09 20:43:14 +10:00
trans_rvd.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvf.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvh.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvi.c.inc target/riscv: rename ext_ifencei to ext_zifencei 2023-11-07 11:02:17 +10:00
trans_rvk.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvm.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvv.c.inc trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*() 2024-02-09 20:43:14 +10:00
trans_rvvk.c.inc target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb' 2024-02-09 20:43:14 +10:00
trans_rvzacas.c.inc target/riscv: Add support for Zacas extension 2024-01-10 18:47:47 +10:00
trans_rvzawrs.c.inc target/riscv: Change gen_set_pc_imm to gen_update_pc 2023-06-13 17:35:20 +10:00
trans_rvzce.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvzfa.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvzfh.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvzicbo.c.inc target/riscv: rename ext_icboz to ext_zicboz 2023-11-07 11:02:17 +10:00
trans_rvzicond.c.inc target/riscv: refactor Zicond support 2023-05-05 10:49:50 +10:00
trans_svinval.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_xthead.c.inc target/riscv: Fix th.dcache.cval1 priviledge check 2024-01-10 18:47:46 +10:00
trans_xventanacondops.c.inc target/riscv: redirect XVentanaCondOps to use the Zicond functions 2023-05-05 10:49:50 +10:00