Alistair Francis 4f5604c41d riscv: plic: Set msi_nonbroken as true ... Set msi_nonbroken as true for the PLIC. According to the comment located here: https://git.qemu.org/?p=qemu.git;a=blob;f=hw/pci/msi.c;h=47d2b0f33c664533b8dbd5cb17faa8e6a01afe1f;hb=HEAD#l38 the msi_nonbroken variable should be set to true even if they don't support MSI. In this case that is what we are doing as we don't support MSI. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reported-by: Andrea Bolognani <abologna@redhat.com> Reported-by: David Abdurachmanov <david.abdurachmanov@gmail.com> Message-Id: <256afbb2da005dc62c159b0f4a4fc0d95c050660.1552679970.git.alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2019-03-18 09:39:57 +01:00
..
Kconfig	riscv/Kconfig: enable PCI_DEVICES	2019-03-11 16:33:49 +01:00
Makefile.objs	hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards	2019-02-05 16:50:20 +01:00
riscv_hart.c	riscv_hart: Fix crash when introspecting the device	2018-07-19 09:05:48 -07:00
riscv_htif.c	hw: Do not include "exec/address-spaces.h" if it is not necessary	2018-06-01 14:15:10 +02:00
sifive_clint.c	RISC-V: Fix CLINT timecmp low 32-bit writes	2018-12-20 12:08:43 -08:00
sifive_e.c	riscv: Ensure the kernel start address is correctly cast	2019-02-11 15:56:22 -08:00
sifive_plic.c	riscv: plic: Set msi_nonbroken as true	2019-03-18 09:39:57 +01:00
sifive_prci.c	SiFive RISC-V PRCI Block	2018-03-07 08:30:28 +13:00
sifive_test.c	SiFive RISC-V Test Finisher	2018-03-07 08:30:28 +13:00
sifive_u.c	riscv: Ensure the kernel start address is correctly cast	2019-02-11 15:56:22 -08:00
sifive_uart.c	sifive_uart: Implement interrupt pending register	2018-12-20 12:08:43 -08:00
spike.c	riscv: Ensure the kernel start address is correctly cast	2019-02-11 15:56:22 -08:00
virt.c	riscv: Ensure the kernel start address is correctly cast	2019-02-11 15:56:22 -08:00