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f21b36a022
Extra word 2 is stored during tcg compile and `decode_save_opc` needs additional argument in order to pass the value. This will be used during unwind to get extra information about instruction like how to massage exceptions. Updated all callsites as well. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/594 Signed-off-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241008225010.1861630-16-debug@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
137 lines
3.9 KiB
C++
137 lines
3.9 KiB
C++
/*
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* RISC-V translation routines for the RV64 Zacas Standard Extension.
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*
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* Copyright (c) 2020-2023 PLCT Lab
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define REQUIRE_ZACAS(ctx) do { \
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if (!ctx->cfg_ptr->ext_zacas) { \
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return false; \
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} \
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} while (0)
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static bool trans_amocas_w(DisasContext *ctx, arg_amocas_w *a)
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{
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REQUIRE_ZACAS(ctx);
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return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TESL);
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}
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static TCGv_i64 get_gpr_pair(DisasContext *ctx, int reg_num)
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{
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TCGv_i64 t;
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assert(get_ol(ctx) == MXL_RV32);
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if (reg_num == 0) {
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return tcg_constant_i64(0);
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}
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t = tcg_temp_new_i64();
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tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]);
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return t;
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}
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static void gen_set_gpr_pair(DisasContext *ctx, int reg_num, TCGv_i64 t)
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{
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assert(get_ol(ctx) == MXL_RV32);
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if (reg_num != 0) {
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#ifdef TARGET_RISCV32
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tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t);
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#else
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tcg_gen_ext32s_i64(cpu_gpr[reg_num], t);
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tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32);
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#endif
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if (get_xl_max(ctx) == MXL_RV128) {
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tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63);
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tcg_gen_sari_tl(cpu_gprh[reg_num + 1], cpu_gpr[reg_num + 1], 63);
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}
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}
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}
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static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic *a, MemOp mop)
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{
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/*
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* Encodings with odd numbered registers specified in rs2 and rd are
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* reserved.
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*/
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if ((a->rs2 | a->rd) & 1) {
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return false;
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}
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TCGv_i64 dest = get_gpr_pair(ctx, a->rd);
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TCGv src1 = get_address(ctx, a->rs1, 0);
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TCGv_i64 src2 = get_gpr_pair(ctx, a->rs2);
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decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
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tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop);
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gen_set_gpr_pair(ctx, a->rd, dest);
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return true;
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}
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static bool trans_amocas_d(DisasContext *ctx, arg_amocas_d *a)
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{
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REQUIRE_ZACAS(ctx);
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switch (get_ol(ctx)) {
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case MXL_RV32:
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return gen_cmpxchg64(ctx, a, MO_ALIGN | MO_TEUQ);
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case MXL_RV64:
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case MXL_RV128:
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return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TEUQ);
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default:
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g_assert_not_reached();
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}
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}
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static bool trans_amocas_q(DisasContext *ctx, arg_amocas_q *a)
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{
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REQUIRE_ZACAS(ctx);
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REQUIRE_64BIT(ctx);
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/*
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* Encodings with odd numbered registers specified in rs2 and rd are
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* reserved.
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*/
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if ((a->rs2 | a->rd) & 1) {
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return false;
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}
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#ifdef TARGET_RISCV64
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TCGv_i128 dest = tcg_temp_new_i128();
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TCGv src1 = get_address(ctx, a->rs1, 0);
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TCGv_i128 src2 = tcg_temp_new_i128();
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TCGv_i64 src2l = get_gpr(ctx, a->rs2, EXT_NONE);
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TCGv_i64 src2h = get_gpr(ctx, a->rs2 == 0 ? 0 : a->rs2 + 1, EXT_NONE);
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TCGv_i64 destl = get_gpr(ctx, a->rd, EXT_NONE);
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TCGv_i64 desth = get_gpr(ctx, a->rd == 0 ? 0 : a->rd + 1, EXT_NONE);
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tcg_gen_concat_i64_i128(src2, src2l, src2h);
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tcg_gen_concat_i64_i128(dest, destl, desth);
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decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
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tcg_gen_atomic_cmpxchg_i128(dest, src1, dest, src2, ctx->mem_idx,
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(MO_ALIGN | MO_TEUO));
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tcg_gen_extr_i128_i64(destl, desth, dest);
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if (a->rd != 0) {
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gen_set_gpr(ctx, a->rd, destl);
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gen_set_gpr(ctx, a->rd + 1, desth);
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}
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#endif
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return true;
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}
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