Richard Henderson e726f65867 tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 ... These defines never should have been added as they were never used. Only 32-bit hosts may have these opcodes and they have them unconditionally. Fixes: 6cb14e4de2 ("tcg/loongarch64: Add the tcg-target.h file") Fixes: fb1f70f368 ("tcg/riscv: Add the tcg-target.h file") Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2025-02-18 08:29:03 -08:00
..
tcg-target-con-set.h	tcg/riscv: Use 'z' constraint	2025-02-18 08:29:03 -08:00
tcg-target-con-str.h	tcg/riscv: Use 'z' constraint	2025-02-18 08:29:03 -08:00
tcg-target-has.h	tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64	2025-02-18 08:29:03 -08:00
tcg-target-mo.h	tcg: Split out tcg-target-mo.h	2025-01-16 20:57:16 -08:00
tcg-target-opc.h.inc	tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc	2025-01-16 20:57:16 -08:00
tcg-target-reg-bits.h	tcg: Split out tcg-target-reg-bits.h	2023-06-05 12:04:28 -07:00
tcg-target.c.inc	tcg/riscv: Use 'z' constraint	2025-02-18 08:29:03 -08:00
tcg-target.h	tcg: Introduce the 'z' constraint for a hardware zero register	2025-02-18 08:29:03 -08:00