qemu/target
Max Filippov 4b37aaa879 target/xtensa: fix ICACHE/DCACHE options detection
Configuration overlay does not explicitly say whether there are ICACHE
and DCACHE in the core. Current code uses XCHAL_[ID]CACHE_WAYS to detect
if corresponding cache option is enabled, but that's not correct: on
cores without cache these macros are defined as 1, not as 0.
Check XCHAL_[ID]CACHE_SIZE instead.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
..
alpha Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
arm Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
cris Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
i386 x86: implement la57 paging mode 2016-12-22 16:01:04 +01:00
lm32 Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
m68k Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
microblaze Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
mips Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
moxie Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
openrisc Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
ppc Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
s390x Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
sh4 Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
sparc Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
tilegx Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
tricore Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
unicore32 Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
xtensa target/xtensa: fix ICACHE/DCACHE options detection 2017-01-15 13:01:56 -08:00