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4b10c8d701
This enables us to remove the static array mapping in the ISA IRQ handler (and the embedded reference to the APB device) by formalising the interrupt wiring via the qdev GPIO API. For more clarity we replace the APB OBIO interrupt numbers with constants designating the interrupt source, and rename isa_irq_handler() to ebus_isa_irq_handler(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
101 lines
2.9 KiB
C
101 lines
2.9 KiB
C
#ifndef PCI_HOST_APB_H
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#define PCI_HOST_APB_H
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#include "qemu-common.h"
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#include "hw/pci/pci_host.h"
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#define IOMMU_NREGS 3
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#define IOMMU_PAGE_SIZE_8K (1ULL << 13)
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#define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1))
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#define IOMMU_PAGE_SIZE_64K (1ULL << 16)
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#define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1))
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#define IOMMU_CTRL 0x0
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#define IOMMU_CTRL_TBW_SIZE (1ULL << 2)
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#define IOMMU_CTRL_MMU_EN (1ULL)
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#define IOMMU_CTRL_TSB_SHIFT 16
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#define IOMMU_BASE 0x8
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#define IOMMU_FLUSH 0x10
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#define IOMMU_TTE_DATA_V (1ULL << 63)
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#define IOMMU_TTE_DATA_SIZE (1ULL << 61)
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#define IOMMU_TTE_DATA_W (1ULL << 1)
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#define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL
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#define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL
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#define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL
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#define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL
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typedef struct IOMMUState {
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AddressSpace iommu_as;
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IOMMUMemoryRegion iommu;
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uint64_t regs[IOMMU_NREGS];
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} IOMMUState;
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#define MAX_IVEC 0x40
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/* OBIO IVEC IRQs */
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#define OBIO_LPT_IRQ 0x22
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#define OBIO_FDD_IRQ 0x27
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#define OBIO_KBD_IRQ 0x29
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#define OBIO_MSE_IRQ 0x2a
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#define OBIO_SER_IRQ 0x2b
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#define TYPE_APB "pbm"
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#define APB_DEVICE(obj) \
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OBJECT_CHECK(APBState, (obj), TYPE_APB)
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#define TYPE_APB_IOMMU_MEMORY_REGION "pbm-iommu-memory-region"
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typedef struct APBState {
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PCIHostState parent_obj;
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hwaddr special_base;
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hwaddr mem_base;
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MemoryRegion apb_config;
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MemoryRegion pci_config;
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MemoryRegion pci_mmio;
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MemoryRegion pci_ioport;
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uint64_t pci_irq_in;
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IOMMUState iommu;
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PCIBridge *bridgeA;
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PCIBridge *bridgeB;
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uint32_t pci_control[16];
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uint32_t pci_irq_map[8];
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uint32_t pci_err_irq_map[4];
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uint32_t obio_irq_map[32];
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qemu_irq ivec_irqs[MAX_IVEC];
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unsigned int irq_request;
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uint32_t reset_control;
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unsigned int nr_resets;
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} APBState;
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typedef struct PBMPCIBridge {
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/*< private >*/
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PCIBridge parent_obj;
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} PBMPCIBridge;
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#define TYPE_PBM_PCI_BRIDGE "pbm-bridge"
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#define PBM_PCI_BRIDGE(obj) \
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OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
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#endif
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