Hao Wu 4a84e85413 hw/adc: Fix CONV bit in NPCM7XX ADC CON register ... The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch fixes that in the module, and also lower the IRQ when the guest is done handling an interrupt event from the ADC module. Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Patrick Venture<venture@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220714182836.89602-4-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2022-07-18 13:20:14 +01:00
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aspeed_adc.c	aspeed/adc: Add AST1030 support	2022-05-02 17:03:02 +02:00
Kconfig	adc: Move the max111x driver to the adc directory	2021-06-17 07:10:32 -05:00
max111x.c	adc: Move the max111x driver to the adc directory	2021-06-17 07:10:32 -05:00
meson.build	hw/adc: Add basic Aspeed ADC model	2021-10-12 08:20:08 +02:00
npcm7xx_adc.c	hw/adc: Fix CONV bit in NPCM7XX ADC CON register	2022-07-18 13:20:14 +01:00
stm32f2xx_adc.c	hw/adc/stm32f2xx_adc: Correct memory region size and access size	2020-06-05 17:23:09 +01:00
trace-events	hw/adc: Add basic Aspeed ADC model	2021-10-12 08:20:08 +02:00
trace.h	hw/adc: Add an ADC module for NPCM7XX	2021-01-12 21:19:02 +00:00
zynq-xadc.c	hw/adc/zynq-xadc: Use qemu_irq typedef	2022-05-19 16:19:02 +01:00