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487967bed6
SNVS contains an RTC which allows Linux to deal correctly with time. This is particularly useful when handling persistent storage which will be done in the next patch. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-7-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
195 lines
4.6 KiB
C
195 lines
4.6 KiB
C
/*
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* i.MX 8M Plus SoC Definitions
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*
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* Copyright (c) 2024, Bernhard Beschow <shentey@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef FSL_IMX8MP_H
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#define FSL_IMX8MP_H
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#include "cpu.h"
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#include "hw/char/imx_serial.h"
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#include "hw/intc/arm_gicv3_common.h"
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#include "hw/misc/imx7_snvs.h"
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#include "hw/misc/imx8mp_analog.h"
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#include "hw/misc/imx8mp_ccm.h"
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#include "qom/object.h"
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#include "qemu/units.h"
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#define TYPE_FSL_IMX8MP "fsl-imx8mp"
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OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mpState, FSL_IMX8MP)
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#define FSL_IMX8MP_RAM_START 0x40000000
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#define FSL_IMX8MP_RAM_SIZE_MAX (8 * GiB)
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enum FslImx8mpConfiguration {
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FSL_IMX8MP_NUM_CPUS = 4,
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FSL_IMX8MP_NUM_IRQS = 160,
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FSL_IMX8MP_NUM_UARTS = 4,
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};
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struct FslImx8mpState {
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DeviceState parent_obj;
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ARMCPU cpu[FSL_IMX8MP_NUM_CPUS];
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GICv3State gic;
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IMX8MPCCMState ccm;
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IMX8MPAnalogState analog;
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IMX7SNVSState snvs;
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IMXSerialState uart[FSL_IMX8MP_NUM_UARTS];
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};
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enum FslImx8mpMemoryRegions {
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FSL_IMX8MP_A53_DAP,
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FSL_IMX8MP_AIPS1_CONFIGURATION,
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FSL_IMX8MP_AIPS2_CONFIGURATION,
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FSL_IMX8MP_AIPS3_CONFIGURATION,
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FSL_IMX8MP_AIPS4_CONFIGURATION,
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FSL_IMX8MP_AIPS5_CONFIGURATION,
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FSL_IMX8MP_ANA_OSC,
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FSL_IMX8MP_ANA_PLL,
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FSL_IMX8MP_ANA_TSENSOR,
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FSL_IMX8MP_APBH_DMA,
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FSL_IMX8MP_ASRC,
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FSL_IMX8MP_AUDIO_BLK_CTRL,
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FSL_IMX8MP_AUDIO_DSP,
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FSL_IMX8MP_AUDIO_XCVR_RX,
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FSL_IMX8MP_AUD_IRQ_STEER,
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FSL_IMX8MP_BOOT_ROM,
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FSL_IMX8MP_BOOT_ROM_PROTECTED,
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FSL_IMX8MP_CAAM,
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FSL_IMX8MP_CAAM_MEM,
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FSL_IMX8MP_CCM,
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FSL_IMX8MP_CSU,
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FSL_IMX8MP_DDR_BLK_CTRL,
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FSL_IMX8MP_DDR_CTL,
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FSL_IMX8MP_DDR_PERF_MON,
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FSL_IMX8MP_DDR_PHY,
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FSL_IMX8MP_DDR_PHY_BROADCAST,
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FSL_IMX8MP_ECSPI1,
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FSL_IMX8MP_ECSPI2,
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FSL_IMX8MP_ECSPI3,
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FSL_IMX8MP_EDMA_CHANNELS,
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FSL_IMX8MP_EDMA_MANAGEMENT_PAGE,
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FSL_IMX8MP_ENET1,
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FSL_IMX8MP_ENET2_TSN,
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FSL_IMX8MP_FLEXCAN1,
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FSL_IMX8MP_FLEXCAN2,
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FSL_IMX8MP_GIC_DIST,
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FSL_IMX8MP_GIC_REDIST,
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FSL_IMX8MP_GPC,
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FSL_IMX8MP_GPIO1,
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FSL_IMX8MP_GPIO2,
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FSL_IMX8MP_GPIO3,
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FSL_IMX8MP_GPIO4,
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FSL_IMX8MP_GPIO5,
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FSL_IMX8MP_GPT1,
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FSL_IMX8MP_GPT2,
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FSL_IMX8MP_GPT3,
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FSL_IMX8MP_GPT4,
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FSL_IMX8MP_GPT5,
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FSL_IMX8MP_GPT6,
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FSL_IMX8MP_GPU2D,
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FSL_IMX8MP_GPU3D,
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FSL_IMX8MP_HDMI_TX,
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FSL_IMX8MP_HDMI_TX_AUDLNK_MSTR,
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FSL_IMX8MP_HSIO_BLK_CTL,
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FSL_IMX8MP_I2C1,
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FSL_IMX8MP_I2C2,
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FSL_IMX8MP_I2C3,
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FSL_IMX8MP_I2C4,
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FSL_IMX8MP_I2C5,
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FSL_IMX8MP_I2C6,
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FSL_IMX8MP_INTERCONNECT,
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FSL_IMX8MP_IOMUXC,
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FSL_IMX8MP_IOMUXC_GPR,
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FSL_IMX8MP_IPS_DEWARP,
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FSL_IMX8MP_ISI,
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FSL_IMX8MP_ISP1,
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FSL_IMX8MP_ISP2,
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FSL_IMX8MP_LCDIF1,
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FSL_IMX8MP_LCDIF2,
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FSL_IMX8MP_MEDIA_BLK_CTL,
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FSL_IMX8MP_MIPI_CSI1,
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FSL_IMX8MP_MIPI_CSI2,
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FSL_IMX8MP_MIPI_DSI1,
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FSL_IMX8MP_MU_1_A,
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FSL_IMX8MP_MU_1_B,
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FSL_IMX8MP_MU_2_A,
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FSL_IMX8MP_MU_2_B,
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FSL_IMX8MP_MU_3_A,
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FSL_IMX8MP_MU_3_B,
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FSL_IMX8MP_NPU,
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FSL_IMX8MP_OCOTP_CTRL,
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FSL_IMX8MP_OCRAM,
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FSL_IMX8MP_OCRAM_S,
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FSL_IMX8MP_PCIE1,
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FSL_IMX8MP_PCIE1_MEM,
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FSL_IMX8MP_PCIE_PHY1,
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FSL_IMX8MP_PDM,
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FSL_IMX8MP_PERFMON1,
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FSL_IMX8MP_PERFMON2,
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FSL_IMX8MP_PWM1,
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FSL_IMX8MP_PWM2,
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FSL_IMX8MP_PWM3,
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FSL_IMX8MP_PWM4,
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FSL_IMX8MP_QOSC,
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FSL_IMX8MP_QSPI,
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FSL_IMX8MP_QSPI1_RX_BUFFER,
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FSL_IMX8MP_QSPI1_TX_BUFFER,
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FSL_IMX8MP_QSPI_MEM,
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FSL_IMX8MP_RAM,
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FSL_IMX8MP_RDC,
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FSL_IMX8MP_SAI1,
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FSL_IMX8MP_SAI2,
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FSL_IMX8MP_SAI3,
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FSL_IMX8MP_SAI5,
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FSL_IMX8MP_SAI6,
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FSL_IMX8MP_SAI7,
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FSL_IMX8MP_SDMA1,
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FSL_IMX8MP_SDMA2,
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FSL_IMX8MP_SDMA3,
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FSL_IMX8MP_SEMAPHORE1,
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FSL_IMX8MP_SEMAPHORE2,
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FSL_IMX8MP_SEMAPHORE_HS,
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FSL_IMX8MP_SNVS_HP,
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FSL_IMX8MP_SPBA1,
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FSL_IMX8MP_SPBA2,
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FSL_IMX8MP_SRC,
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FSL_IMX8MP_SYSCNT_CMP,
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FSL_IMX8MP_SYSCNT_CTRL,
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FSL_IMX8MP_SYSCNT_RD,
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FSL_IMX8MP_TCM_DTCM,
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FSL_IMX8MP_TCM_ITCM,
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FSL_IMX8MP_TZASC,
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FSL_IMX8MP_UART1,
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FSL_IMX8MP_UART2,
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FSL_IMX8MP_UART3,
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FSL_IMX8MP_UART4,
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FSL_IMX8MP_USB1,
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FSL_IMX8MP_USB2,
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FSL_IMX8MP_USDHC1,
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FSL_IMX8MP_USDHC2,
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FSL_IMX8MP_USDHC3,
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FSL_IMX8MP_VPU,
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FSL_IMX8MP_VPU_BLK_CTRL,
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FSL_IMX8MP_VPU_G1_DECODER,
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FSL_IMX8MP_VPU_G2_DECODER,
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FSL_IMX8MP_VPU_VC8000E_ENCODER,
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FSL_IMX8MP_WDOG1,
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FSL_IMX8MP_WDOG2,
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FSL_IMX8MP_WDOG3,
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};
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enum FslImx8mpIrqs {
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FSL_IMX8MP_UART1_IRQ = 26,
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FSL_IMX8MP_UART2_IRQ = 27,
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FSL_IMX8MP_UART3_IRQ = 28,
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FSL_IMX8MP_UART4_IRQ = 29,
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FSL_IMX8MP_UART5_IRQ = 30,
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FSL_IMX8MP_UART6_IRQ = 16,
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};
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#endif /* FSL_IMX8MP_H */
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