Alex Bennée 47a2def453 accel/tcg: remove link between guest ram and TCG cache size ... Basing the TB cache size on the ram_size was always a little heuristic and was broken by a1b18df9a4 which caused ram_size not to be fully realised at the time we initialise the TCG translation cache. The current DEFAULT_CODE_GEN_BUFFER_SIZE may still be a little small but follow-up patches will address that. Fixes: a1b18df9a4 Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-Id: <20200228192415.19867-3-alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2020-02-28 17:42:48 -08:00
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kvm	Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEAD	2020-02-25 13:41:48 +01:00
stubs	kvm: Introduce KVM irqchip change notifier	2019-11-26 10:11:30 +11:00
tcg	accel/tcg: remove link between guest ram and TCG cache size	2020-02-28 17:42:48 -08:00
accel.c	accel: Introduce the current_accel() wrapper	2020-01-24 20:59:11 +01:00
Makefile.objs	accel: compile accel/accel.c just once	2019-12-17 19:32:25 +01:00
qtest.c	qtest: Don't compile qtest accel on non-POSIX systems	2019-05-02 16:56:33 +02:00