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ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even tough they don't have the TTBCR register. See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile Version:A.c section C1.2. Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20221206102504.165775-5-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| avr | ||
| cris | ||
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| i386 | ||
| loongarch | ||
| m68k | ||
| microblaze | ||
| mips | ||
| nios2 | ||
| openrisc | ||
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| sh4 | ||
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| tricore | ||
| xtensa | ||
| Kconfig | ||
| meson.build | ||