qemu/target/sparc/insns.decode
Richard Henderson 45196ea4f4 target/sparc: Move FBPfcc and FBfcc to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25 01:01:12 -07:00

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# SPDX-License-Identifier: LGPL-2.0+
#
# Sparc instruction decode definitions.
# Copyright (c) 2023 Richard Henderson <rth@twiddle.net>
&bcc i a cond cc
BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc
Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0
FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc
FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0
%d16 20:s2 0:14
BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16
NCP 00 - ---- 111 ---------------------- # CBcc
CALL 01 i:s30