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Indirect branches, plus eret and bret optionally raise an exception when branching to a misaligned address. The exception is required when an mmu is enabled, but enable it always because the fallback behaviour is not documented (though presumably it discards low bits). For the purposes of the linux-user cpu loop, if EXCP_UNALIGN (misaligned data) were to arrive, it would be treated the same as EXCP_UNALIGND (misaligned destination). See the !defined(CONFIG_NIOS2_ALIGNMENT_TRAP) block in kernel/traps.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-53-richard.henderson@linaro.org>
148 lines
4.9 KiB
C
148 lines
4.9 KiB
C
/*
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* qemu user cpu loop
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu.h"
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#include "user-internals.h"
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#include "cpu_loop-common.h"
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#include "signal-common.h"
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void cpu_loop(CPUNios2State *env)
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{
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CPUState *cs = env_cpu(env);
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int trapnr, ret;
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for (;;) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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switch (trapnr) {
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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case EXCP_DIV:
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force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc);
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break;
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case EXCP_UNALIGN:
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case EXCP_UNALIGND:
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force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN,
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env->ctrl[CR_BADADDR]);
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break;
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case EXCP_TRAP:
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/*
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* TODO: This advance should be done in the translator, as
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* hardware produces an advanced pc as part of all exceptions.
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*/
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env->pc += 4;
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switch (env->error_code) {
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case 0:
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qemu_log_mask(CPU_LOG_INT, "\nSyscall\n");
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ret = do_syscall(env, env->regs[2],
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env->regs[4], env->regs[5], env->regs[6],
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env->regs[7], env->regs[8], env->regs[9],
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0, 0);
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if (ret == -QEMU_ESIGRETURN) {
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/* rt_sigreturn has set all state. */
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break;
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}
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if (ret == -QEMU_ERESTARTSYS) {
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env->pc -= 4;
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break;
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}
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/*
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* See the code after translate_rc_and_ret: all negative
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* values are errors (aided by userspace restricted to 2G),
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* errno is returned positive in r2, and error indication
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* is a boolean in r7.
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*/
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env->regs[2] = abs(ret);
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env->regs[7] = ret < 0;
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break;
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case 1:
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qemu_log_mask(CPU_LOG_INT, "\nTrap 1\n");
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force_sig_fault(TARGET_SIGUSR1, 0, env->pc);
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break;
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case 2:
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qemu_log_mask(CPU_LOG_INT, "\nTrap 2\n");
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force_sig_fault(TARGET_SIGUSR2, 0, env->pc);
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break;
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case 31:
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qemu_log_mask(CPU_LOG_INT, "\nTrap 31\n");
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/* Match kernel's breakpoint_c(). */
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env->pc -= 4;
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force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
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break;
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default:
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qemu_log_mask(CPU_LOG_INT, "\nTrap %d\n", env->error_code);
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, env->pc);
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break;
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case 16: /* QEMU specific, for __kuser_cmpxchg */
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{
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abi_ptr g = env->regs[4];
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uint32_t *h, n, o;
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if (g & 0x3) {
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force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, g);
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break;
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}
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ret = page_get_flags(g);
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if (!(ret & PAGE_VALID)) {
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force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, g);
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break;
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}
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if (!(ret & PAGE_READ) || !(ret & PAGE_WRITE)) {
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force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_ACCERR, g);
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break;
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}
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h = g2h(cs, g);
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o = env->regs[5];
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n = env->regs[6];
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env->regs[2] = qatomic_cmpxchg(h, o, n) - o;
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}
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break;
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}
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break;
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case EXCP_DEBUG:
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force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
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break;
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default:
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EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
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trapnr);
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abort();
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}
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process_pending_signals(env);
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}
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}
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void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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{
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env->regs[R_SP] = regs->sp;
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env->pc = regs->ea;
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}
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