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qemu/target/riscv/insn_trans
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Richard Henderson 40eaa47361 target/riscv: Generate nanboxed results from trans_rvf.inc.c 
Make sure that all results from inline single-precision scalar
operations are properly nan-boxed to 64-bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-4-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-08-21 22:37:55 -07:00
..
trans_privileged.c.inc meson: rename included C source files to .c.inc 2020-08-21 06:18:30 -04:00
trans_rva.c.inc meson: rename included C source files to .c.inc 2020-08-21 06:18:30 -04:00
trans_rvd.c.inc meson: rename included C source files to .c.inc 2020-08-21 06:18:30 -04:00
trans_rvf.c.inc target/riscv: Generate nanboxed results from trans_rvf.inc.c 2020-08-21 22:37:55 -07:00
trans_rvh.c.inc meson: rename included C source files to .c.inc 2020-08-21 06:18:30 -04:00
trans_rvi.c.inc meson: rename included C source files to .c.inc 2020-08-21 06:18:30 -04:00
trans_rvm.c.inc meson: rename included C source files to .c.inc 2020-08-21 06:18:30 -04:00
trans_rvv.c.inc meson: rename included C source files to .c.inc 2020-08-21 06:18:30 -04:00