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40b44316d8
To test the RISC-V IOMMU emulation we'll use its PCI representation. Create a new 'riscv-iommu-pci' libqos device that will be present with CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this device will only be consumed by the RISC-V libqos machine. Start with basic tests: a PCI sanity check and a reset state register test. The reset test was taken from the RISC-V IOMMU spec chapter 5.2, "Reset behavior". More tests will be added later. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241016204038.649340-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
85 lines
3 KiB
C
85 lines
3 KiB
C
/*
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* QTest testcase for RISC-V IOMMU
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*
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* Copyright (c) 2024 Ventana Micro Systems Inc.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at your
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* option) any later version. See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "libqtest-single.h"
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#include "qemu/module.h"
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#include "libqos/qgraph.h"
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#include "libqos/riscv-iommu.h"
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#include "hw/pci/pci_regs.h"
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static uint32_t riscv_iommu_read_reg32(QRISCVIOMMU *r_iommu, int reg_offset)
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{
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return qpci_io_readl(&r_iommu->dev, r_iommu->reg_bar, reg_offset);
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}
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static uint64_t riscv_iommu_read_reg64(QRISCVIOMMU *r_iommu, int reg_offset)
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{
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return qpci_io_readq(&r_iommu->dev, r_iommu->reg_bar, reg_offset);
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}
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static void test_pci_config(void *obj, void *data, QGuestAllocator *t_alloc)
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{
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QRISCVIOMMU *r_iommu = obj;
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QPCIDevice *dev = &r_iommu->dev;
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uint16_t vendorid, deviceid, classid;
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vendorid = qpci_config_readw(dev, PCI_VENDOR_ID);
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deviceid = qpci_config_readw(dev, PCI_DEVICE_ID);
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classid = qpci_config_readw(dev, PCI_CLASS_DEVICE);
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g_assert_cmpuint(vendorid, ==, RISCV_IOMMU_PCI_VENDOR_ID);
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g_assert_cmpuint(deviceid, ==, RISCV_IOMMU_PCI_DEVICE_ID);
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g_assert_cmpuint(classid, ==, RISCV_IOMMU_PCI_DEVICE_CLASS);
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}
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static void test_reg_reset(void *obj, void *data, QGuestAllocator *t_alloc)
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{
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QRISCVIOMMU *r_iommu = obj;
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uint64_t cap;
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uint32_t reg;
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cap = riscv_iommu_read_reg64(r_iommu, RISCV_IOMMU_REG_CAP);
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g_assert_cmpuint(cap & RISCV_IOMMU_CAP_VERSION, ==, 0x10);
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reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_CQCSR);
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g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CQEN, ==, 0);
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g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CIE, ==, 0);
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g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CQON, ==, 0);
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g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_BUSY, ==, 0);
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reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_FQCSR);
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g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FQEN, ==, 0);
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g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FIE, ==, 0);
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g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FQON, ==, 0);
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g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_BUSY, ==, 0);
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reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_PQCSR);
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g_assert_cmpuint(reg & RISCV_IOMMU_PQCSR_PQEN, ==, 0);
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g_assert_cmpuint(reg & RISCV_IOMMU_PQCSR_PIE, ==, 0);
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g_assert_cmpuint(reg & RISCV_IOMMU_PQCSR_PQON, ==, 0);
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g_assert_cmpuint(reg & RISCV_IOMMU_PQCSR_BUSY, ==, 0);
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reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_DDTP);
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g_assert_cmpuint(reg & RISCV_IOMMU_DDTP_BUSY, ==, 0);
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g_assert_cmpuint(reg & RISCV_IOMMU_DDTP_MODE, ==,
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RISCV_IOMMU_DDTP_MODE_OFF);
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reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_IPSR);
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g_assert_cmpuint(reg, ==, 0);
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}
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static void register_riscv_iommu_test(void)
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{
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qos_add_test("pci_config", "riscv-iommu-pci", test_pci_config, NULL);
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qos_add_test("reg_reset", "riscv-iommu-pci", test_reg_reset, NULL);
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}
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libqos_init(register_riscv_iommu_test);
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