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9a2a5f1b63
The TCG IR sequence: mov_i32 tmp97,$0xc4240000 dead: 1 pref=0xffffffff mov_i32 tmp98,$0x0 pref=0xffffffff rotr_i32 tmp97,tmp97,tmp98 dead: 1 2 pref=0xffffffff was translated to `slwi r15, r14, 0` instead of `slwi r14, r14, 0` due to SH field overflow. SH field is 5 bits, and tcg_out_rlw is called in some situations with `32-n`, when `n` is 0 it results in an overflow to RA field. This commit prevents overflow of that field and adds debug assertions for the other fields Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Dani Szebenyi <szedani@linux.ibm.com> Message-ID: <20241022133535.69351-2-szedani@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
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| aarch64 | ||
| arm | ||
| i386 | ||
| loongarch64 | ||
| mips | ||
| ppc | ||
| riscv | ||
| s390x | ||
| sparc64 | ||
| tci | ||
| debuginfo.c | ||
| meson.build | ||
| optimize.c | ||
| perf.c | ||
| region.c | ||
| tcg-common.c | ||
| tcg-internal.h | ||
| tcg-ldst.c.inc | ||
| tcg-op-gvec.c | ||
| tcg-op-ldst.c | ||
| tcg-op-vec.c | ||
| tcg-op.c | ||
| tcg-pool.c.inc | ||
| tcg.c | ||
| tci.c | ||