Jonathan Cameron 14bd0f3865 hw/mem/cxl-type3: Add properties to control link speed and width ... To establish performance characteristics of a CXL device when used via a particular CXL topology (root ports, switches, end points) it is necessary to set the appropriate link speed and width in the PCI Express capability structure. Provide x-speed and x-link properties for this. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240916173518.1843023-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2024-11-04 16:03:24 -05:00
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cxl.h	hw/cxl/mbox: Add Physical Switch Identify command.	2023-11-07 03:39:11 -05:00
cxl_cdat.h	hw/mem/cxl_type3: Fix problem with g_steal_pointer()	2024-03-09 18:56:37 +03:00
cxl_component.h	hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return boolean	2024-04-25 12:48:12 +02:00
cxl_device.h	hw/mem/cxl-type3: Add properties to control link speed and width	2024-11-04 16:03:24 -05:00
cxl_events.h	hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents	2024-07-01 17:16:04 -04:00
cxl_host.h	hw/cxl: Clean up includes	2023-02-08 07:16:23 +01:00
cxl_mailbox.h	cxl/mailbox: move mailbox effect definitions to a header	2024-07-21 14:31:59 -04:00
cxl_pci.h	hw/cxl: Fix missing reserved data in CXL Device DVSEC	2024-03-12 17:59:48 -04:00