mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-09 02:24:58 -06:00
3966582099
Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the translator to reject doubleword instructions in LA32 mode for example. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-5-gaosong@loongson.cn> Message-Id: <20230822071405.35386-5-philmd@linaro.org>
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
/*
|
|
* LoongArch translation routines.
|
|
*
|
|
* Copyright (c) 2021 Loongson Technology Corporation Limited
|
|
*/
|
|
|
|
#ifndef TARGET_LOONGARCH_TRANSLATE_H
|
|
#define TARGET_LOONGARCH_TRANSLATE_H
|
|
|
|
#include "exec/translator.h"
|
|
|
|
#define TRANS(NAME, FUNC, ...) \
|
|
static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
|
|
{ return FUNC(ctx, a, __VA_ARGS__); }
|
|
|
|
/*
|
|
* If an operation is being performed on less than TARGET_LONG_BITS,
|
|
* it may require the inputs to be sign- or zero-extended; which will
|
|
* depend on the exact operation being performed.
|
|
*/
|
|
typedef enum {
|
|
EXT_NONE,
|
|
EXT_SIGN,
|
|
EXT_ZERO,
|
|
} DisasExtend;
|
|
|
|
typedef struct DisasContext {
|
|
DisasContextBase base;
|
|
target_ulong page_start;
|
|
uint32_t opcode;
|
|
uint16_t mem_idx;
|
|
uint16_t plv;
|
|
int vl; /* Vector length */
|
|
TCGv zero;
|
|
bool la64; /* LoongArch64 mode */
|
|
bool va32; /* 32-bit virtual address */
|
|
} DisasContext;
|
|
|
|
void generate_exception(DisasContext *ctx, int excp);
|
|
|
|
extern TCGv cpu_gpr[32], cpu_pc;
|
|
extern TCGv_i32 cpu_fscr0;
|
|
extern TCGv_i64 cpu_fpr[32];
|
|
|
|
#endif
|