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38ba38d87d
Introduce a new ast2700 INTCIO class to support AST2700 INTCIO.
Added new register definitions for INTCIO, including enable and status
registers for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTCIO, supporting six input pins and six
output pins, aligning with the newly defined registers.
Implemented "aspeed_intcio_read" and "aspeed_intcio_write" to handle
INTCIO-specific register access.
To GICINT196 |
ETH1 |-----------| |--------------------------|
-------->|0 | | INTCIO |
ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|
-------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|
ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|
-------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|
UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|
-------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|
UART1 | 22| |--------------------------|
-------->|8 23|
UART2 | 24|
-------->|9 25|
UART3 | 26|
---------|10 27|
UART5 | 28|
-------->|11 29|
UART6 | |
-------->|12 30|
UART7 | 31|
-------->|13 |
UART8 | OR[0:31] |
-------->|14 |
UART9 | |
-------->|15 |
UART10 | |
-------->|16 |
UART11 | |
-------->|17 |
UART12 | |
-------->|18 |
|-----------|
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-18-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
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| .. | ||
| accel | ||
| authz | ||
| block | ||
| chardev | ||
| crypto | ||
| disas | ||
| exec | ||
| fpu | ||
| gdbstub | ||
| hw | ||
| io | ||
| libdecnumber | ||
| migration | ||
| monitor | ||
| net | ||
| qapi | ||
| qemu | ||
| qobject | ||
| qom | ||
| scsi | ||
| semihosting | ||
| standard-headers | ||
| system | ||
| tcg | ||
| ui | ||
| user | ||
| elf.h | ||
| glib-compat.h | ||
| qemu-io.h | ||
| qemu-main.h | ||