mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-07-31 06:13:53 -06:00
55c136599f
When riscv_load_firmware() loads an ELF, the ELF segment addresses are used, not the passed-in firmware_load_addr. The machine models assume the firmware entry point is what they provided for firmware_load_addr, and use that address to generate the boot ROM, so if the ELF is linked at any other address, the boot ROM will jump to empty memory. Pass back the ELF entry point to use when generating the boot ROM, so the boot ROM can jump to firmware loaded anywhere in RAM. For example, on the virt machine, this allows using an OpenSBI fw_dynamic.elf built with FW_TEXT_START values other than 0x80000000. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240817002651.3209701-1-samuel.holland@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
66 lines
3 KiB
C
66 lines
3 KiB
C
/*
|
|
* QEMU RISC-V Boot Helper
|
|
*
|
|
* Copyright (c) 2017 SiFive, Inc.
|
|
* Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2 or later, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along with
|
|
* this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#ifndef RISCV_BOOT_H
|
|
#define RISCV_BOOT_H
|
|
|
|
#include "exec/cpu-defs.h"
|
|
#include "hw/loader.h"
|
|
#include "hw/riscv/riscv_hart.h"
|
|
|
|
#define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin"
|
|
#define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin"
|
|
|
|
bool riscv_is_32bit(RISCVHartArrayState *harts);
|
|
|
|
char *riscv_plic_hart_config_string(int hart_count);
|
|
|
|
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
|
|
target_ulong firmware_end_addr);
|
|
target_ulong riscv_find_and_load_firmware(MachineState *machine,
|
|
const char *default_machine_firmware,
|
|
hwaddr *firmware_load_addr,
|
|
symbol_fn_t sym_cb);
|
|
const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
|
|
char *riscv_find_firmware(const char *firmware_filename,
|
|
const char *default_machine_firmware);
|
|
target_ulong riscv_load_firmware(const char *firmware_filename,
|
|
hwaddr *firmware_load_addr,
|
|
symbol_fn_t sym_cb);
|
|
target_ulong riscv_load_kernel(MachineState *machine,
|
|
RISCVHartArrayState *harts,
|
|
target_ulong firmware_end_addr,
|
|
bool load_initrd,
|
|
symbol_fn_t sym_cb);
|
|
uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
|
|
MachineState *ms);
|
|
void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
|
|
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
|
|
hwaddr saddr,
|
|
hwaddr rom_base, hwaddr rom_size,
|
|
uint64_t kernel_entry,
|
|
uint64_t fdt_load_addr);
|
|
void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
|
|
hwaddr rom_size,
|
|
uint32_t reset_vec_size,
|
|
uint64_t kernel_entry);
|
|
void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr);
|
|
void riscv_setup_firmware_boot(MachineState *machine);
|
|
|
|
#endif /* RISCV_BOOT_H */
|