Bin Meng 382cb4392f riscv: sifive_u: Do not create hard-coded phandles in DT ... At present the cpu, plic and ethclk nodes' phandles are hard-coded to 1/2/3 in DT. If we configure more than 1 cpu for the machine, all cpu nodes' phandles conflict with each other as they are all 1. Fix it by removing the hardcode. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-06-27 02:47:06 -07:00
..
Kconfig	kconfig: add CONFIG_MSI_NONBROKEN	2019-03-18 09:39:57 +01:00
Makefile.objs	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
riscv_hart.c	Include qemu/module.h where needed, drop it from qemu-common.h	2019-06-12 13:18:33 +02:00
riscv_htif.c	hw: Do not include "exec/address-spaces.h" if it is not necessary	2018-06-01 14:15:10 +02:00
sifive_clint.c	Include qemu/module.h where needed, drop it from qemu-common.h	2019-06-12 13:18:33 +02:00
sifive_e.c	RISC-V: Fix a memory leak when realizing a sifive_e	2019-06-23 23:44:42 -07:00
sifive_gpio.c	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
sifive_plic.c	Include qemu/module.h where needed, drop it from qemu-common.h	2019-06-12 13:18:33 +02:00
sifive_prci.c	sifive_prci: Read and write PRCI registers	2019-06-23 23:44:41 -07:00
sifive_test.c	Include qemu/module.h where needed, drop it from qemu-common.h	2019-06-12 13:18:33 +02:00
sifive_u.c	riscv: sifive_u: Do not create hard-coded phandles in DT	2019-06-27 02:47:06 -07:00
sifive_uart.c	riscv: sifive_uart: Generate TX interrupt	2019-03-19 05:18:28 -07:00
spike.c	riscv: spike: Add a generic spike machine	2019-05-24 12:09:24 -07:00
trace-events	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
virt.c	riscv: virt: Add cpu-topology DT node.	2019-06-25 22:37:08 -07:00