Daniel Henrique Barboza 3739732e75 target/riscv: add shcounterenw ... shcounterenw is defined in RVA22 as: "For any hpmcounter that is not read-only zero, the corresponding bit in hcounteren must be writable." This is always true in TCG so let's claim support for it. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241218114026.1652352-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2025-01-19 09:44:34 +10:00
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acpi	target/riscv: add shcounterenw	2025-01-19 09:44:34 +10:00
hex-loader	tests: Move tests/hex-loader-check-data/ to tests/data/hex-loader/	2018-11-05 13:23:46 -05:00
qobject	target/cris: Remove the deprecated CRIS target	2024-09-13 20:11:13 +02:00
smbios	tests: smbios: add test for legacy mode CLI options	2024-03-18 08:42:45 -04:00
uefi-boot-images	tests/data/uefi-boot-images: Add RISC-V ISO image	2024-07-03 18:14:06 -04:00
test-qga-config	qga: Replace 'blacklist' command line and config file options by 'block-rpcs'	2022-09-20 12:37:00 +02:00
test-qga-os-release	test-qga: add test for guest-get-osinfo	2017-07-18 05:49:01 -05:00