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3504f104ea
CPU_TLB_DYN_*_BITS definitions are only used by accel/tcg/cputlb.c and accel/tcg/translate-all.c. Move them to accel/tcg/tb-internal.h. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250305191859.71608-1-philmd@linaro.org>
80 lines
2.4 KiB
C
80 lines
2.4 KiB
C
/*
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* TranslationBlock internal declarations (target specific)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#ifndef ACCEL_TCG_TB_INTERNAL_TARGET_H
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#define ACCEL_TCG_TB_INTERNAL_TARGET_H
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#include "exec/cpu-all.h"
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#include "exec/exec-all.h"
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#include "exec/translation-block.h"
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#ifdef CONFIG_SOFTMMU
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#define CPU_TLB_DYN_MIN_BITS 6
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#define CPU_TLB_DYN_DEFAULT_BITS 8
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# if HOST_LONG_BITS == 32
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/* Make sure we do not require a double-word shift for the TLB load */
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# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
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# else /* HOST_LONG_BITS == 64 */
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/*
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* Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) ==
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* 2**34 == 16G of address space. This is roughly what one would expect a
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* TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel
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* Skylake's Level-2 STLB has 16 1G entries.
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* Also, make sure we do not size the TLB past the guest's address space.
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*/
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# ifdef TARGET_PAGE_BITS_VARY
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# define CPU_TLB_DYN_MAX_BITS \
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MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
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# else
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# define CPU_TLB_DYN_MAX_BITS \
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MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS)
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# endif
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# endif
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#endif /* CONFIG_SOFTMMU */
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#ifdef CONFIG_USER_ONLY
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#include "user/page-protection.h"
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/*
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* For user-only, page_protect sets the page read-only.
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* Since most execution is already on read-only pages, and we'd need to
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* account for other TBs on the same page, defer undoing any page protection
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* until we receive the write fault.
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*/
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static inline void tb_lock_page0(tb_page_addr_t p0)
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{
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page_protect(p0);
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}
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static inline void tb_lock_page1(tb_page_addr_t p0, tb_page_addr_t p1)
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{
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page_protect(p1);
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}
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static inline void tb_unlock_page1(tb_page_addr_t p0, tb_page_addr_t p1) { }
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static inline void tb_unlock_pages(TranslationBlock *tb) { }
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#else
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void tb_lock_page0(tb_page_addr_t);
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void tb_lock_page1(tb_page_addr_t, tb_page_addr_t);
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void tb_unlock_page1(tb_page_addr_t, tb_page_addr_t);
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void tb_unlock_pages(TranslationBlock *);
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#endif
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#ifdef CONFIG_SOFTMMU
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void tb_invalidate_phys_range_fast(ram_addr_t ram_addr,
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unsigned size,
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uintptr_t retaddr);
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#endif /* CONFIG_SOFTMMU */
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bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc);
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void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr);
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#endif
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