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346160cbf2
Currently, the Aspeed machines allocate a ram container region in which the machine ram region is mapped. See commitad1a978218("aspeed: add a RAM memory region container"). An extra region is mapped after ram in the ram container to catch invalid access done by FW. That's how FW determines the size of ram. See commitebe31c0a8e("aspeed: add a max_ram_size property to the memory controller"). Let's move all the logic under the SoC where it should be. It will also ease the work on multi SoC support. Reviewed-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20220623202123.3972977-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
171 lines
4 KiB
C
171 lines
4 KiB
C
/*
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* ASPEED SoC family
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_SOC_H
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#define ASPEED_SOC_H
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#include "hw/cpu/a15mpcore.h"
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#include "hw/arm/armv7m.h"
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#include "hw/intc/aspeed_vic.h"
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#include "hw/misc/aspeed_scu.h"
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#include "hw/adc/aspeed_adc.h"
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#include "hw/misc/aspeed_sdmc.h"
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#include "hw/misc/aspeed_xdma.h"
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#include "hw/timer/aspeed_timer.h"
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#include "hw/rtc/aspeed_rtc.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "hw/misc/aspeed_i3c.h"
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#include "hw/ssi/aspeed_smc.h"
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#include "hw/misc/aspeed_hace.h"
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#include "hw/misc/aspeed_sbc.h"
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#include "hw/watchdog/wdt_aspeed.h"
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#include "hw/net/ftgmac100.h"
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#include "target/arm/cpu.h"
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#include "hw/gpio/aspeed_gpio.h"
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#include "hw/sd/aspeed_sdhci.h"
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#include "hw/usb/hcd-ehci.h"
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#include "qom/object.h"
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#include "hw/misc/aspeed_lpc.h"
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#define ASPEED_SPIS_NUM 2
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#define ASPEED_EHCIS_NUM 2
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#define ASPEED_WDTS_NUM 4
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#define ASPEED_CPUS_NUM 2
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#define ASPEED_MACS_NUM 4
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struct AspeedSoCState {
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/*< private >*/
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DeviceState parent;
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/*< public >*/
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ARMCPU cpu[ASPEED_CPUS_NUM];
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A15MPPrivState a7mpcore;
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ARMv7MState armv7m;
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MemoryRegion *dram_mr;
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MemoryRegion dram_container;
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MemoryRegion sram;
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AspeedVICState vic;
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AspeedRtcState rtc;
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AspeedTimerCtrlState timerctrl;
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AspeedI2CState i2c;
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AspeedI3CState i3c;
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AspeedSCUState scu;
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AspeedHACEState hace;
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AspeedXDMAState xdma;
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AspeedADCState adc;
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AspeedSMCState fmc;
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AspeedSMCState spi[ASPEED_SPIS_NUM];
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EHCISysBusState ehci[ASPEED_EHCIS_NUM];
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AspeedSBCState sbc;
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AspeedSDMCState sdmc;
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AspeedWDTState wdt[ASPEED_WDTS_NUM];
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FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
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AspeedMiiState mii[ASPEED_MACS_NUM];
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AspeedGPIOState gpio;
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AspeedGPIOState gpio_1_8v;
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AspeedSDHCIState sdhci;
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AspeedSDHCIState emmc;
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AspeedLPCState lpc;
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uint32_t uart_default;
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Clock *sysclk;
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};
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#define TYPE_ASPEED_SOC "aspeed-soc"
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OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
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struct AspeedSoCClass {
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DeviceClass parent_class;
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const char *name;
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const char *cpu_type;
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uint32_t silicon_rev;
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uint64_t sram_size;
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int spis_num;
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int ehcis_num;
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int wdts_num;
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int macs_num;
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int uarts_num;
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const int *irqmap;
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const hwaddr *memmap;
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uint32_t num_cpus;
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qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
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};
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enum {
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ASPEED_DEV_IOMEM,
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ASPEED_DEV_UART1,
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ASPEED_DEV_UART2,
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ASPEED_DEV_UART3,
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ASPEED_DEV_UART4,
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ASPEED_DEV_UART5,
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ASPEED_DEV_UART6,
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ASPEED_DEV_UART7,
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ASPEED_DEV_UART8,
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ASPEED_DEV_UART9,
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ASPEED_DEV_UART10,
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ASPEED_DEV_UART11,
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ASPEED_DEV_UART12,
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ASPEED_DEV_UART13,
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ASPEED_DEV_VUART,
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ASPEED_DEV_FMC,
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ASPEED_DEV_SPI1,
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ASPEED_DEV_SPI2,
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ASPEED_DEV_EHCI1,
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ASPEED_DEV_EHCI2,
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ASPEED_DEV_VIC,
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ASPEED_DEV_SDMC,
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ASPEED_DEV_SCU,
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ASPEED_DEV_ADC,
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ASPEED_DEV_SBC,
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ASPEED_DEV_EMMC_BC,
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ASPEED_DEV_VIDEO,
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ASPEED_DEV_SRAM,
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ASPEED_DEV_SDHCI,
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ASPEED_DEV_GPIO,
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ASPEED_DEV_GPIO_1_8V,
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ASPEED_DEV_RTC,
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ASPEED_DEV_TIMER1,
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ASPEED_DEV_TIMER2,
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ASPEED_DEV_TIMER3,
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ASPEED_DEV_TIMER4,
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ASPEED_DEV_TIMER5,
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ASPEED_DEV_TIMER6,
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ASPEED_DEV_TIMER7,
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ASPEED_DEV_TIMER8,
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ASPEED_DEV_WDT,
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ASPEED_DEV_PWM,
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ASPEED_DEV_LPC,
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ASPEED_DEV_IBT,
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ASPEED_DEV_I2C,
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ASPEED_DEV_ETH1,
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ASPEED_DEV_ETH2,
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ASPEED_DEV_ETH3,
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ASPEED_DEV_ETH4,
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ASPEED_DEV_MII1,
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ASPEED_DEV_MII2,
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ASPEED_DEV_MII3,
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ASPEED_DEV_MII4,
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ASPEED_DEV_SDRAM,
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ASPEED_DEV_XDMA,
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ASPEED_DEV_EMMC,
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ASPEED_DEV_KCS,
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ASPEED_DEV_HACE,
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ASPEED_DEV_DPMCU,
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ASPEED_DEV_DP,
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ASPEED_DEV_I3C,
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};
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qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
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void aspeed_soc_uart_init(AspeedSoCState *s);
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bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
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#endif /* ASPEED_SOC_H */
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