mirror of
https://github.com/Motorhead1991/qemu.git
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32a97c5d05
- Add TCGOP_TYPE, TCGOP_FLAGS.
- Pass type and flags to tcg_op_supported, tcg_target_op_def.
- Split out tcg-target-has.h and unexport from tcg.h.
- Reorg constraint processing; constify TCGOpDef.
- Make extract, sextract, deposit opcodes mandatory.
- Merge ext{8,16,32}{s,u} opcodes into {s}extract.
tcg/mips: Expand bswap unconditionally
tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64
tcg/riscv: Use BEXTI for single-bit extractions
tcg/sparc64: Use SRA, SRL for {s}extract_i64
disas/riscv: Guard dec->cfg dereference for host disassemble
util/cpuinfo-riscv: Detect Zbs
accel/tcg: Call tcg_tb_insert() for one-insn TBs
linux-user: Add missing /proc/cpuinfo fields for sparc
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Merge tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu into staging
tcg:
- Add TCGOP_TYPE, TCGOP_FLAGS.
- Pass type and flags to tcg_op_supported, tcg_target_op_def.
- Split out tcg-target-has.h and unexport from tcg.h.
- Reorg constraint processing; constify TCGOpDef.
- Make extract, sextract, deposit opcodes mandatory.
- Merge ext{8,16,32}{s,u} opcodes into {s}extract.
tcg/mips: Expand bswap unconditionally
tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64
tcg/riscv: Use BEXTI for single-bit extractions
tcg/sparc64: Use SRA, SRL for {s}extract_i64
disas/riscv: Guard dec->cfg dereference for host disassemble
util/cpuinfo-riscv: Detect Zbs
accel/tcg: Call tcg_tb_insert() for one-insn TBs
linux-user: Add missing /proc/cpuinfo fields for sparc
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# gpg: Signature made Fri 17 Jan 2025 13:19:33 EST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu: (68 commits)
softfloat: Constify helpers returning float_status field
accel/tcg: Call tcg_tb_insert() for one-insn TBs
tcg: Document tb_lookup() and tcg_tb_lookup()
linux-user: Add missing /proc/cpuinfo fields for sparc
tcg/riscv: Use BEXTI for single-bit extractions
util/cpuinfo-riscv: Detect Zbs
tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64}
tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}
tcg/tci: Remove assertions for deposit and extract
tcg/tci: Provide TCG_TARGET_{s}extract_valid
tcg/sparc64: Use SRA, SRL for {s}extract_i64
tcg/s390x: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64
tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/ppc: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/mips: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/loongarch64: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/arm: Add full [US]XT[BH] into {s}extract
tcg/aarch64: Expand extract with offset 0 with andi
tcg/aarch64: Provide TCG_TARGET_{s}extract_valid
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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| .. | ||
| aarch64 | ||
| alpha | ||
| arm | ||
| generic | ||
| hexagon | ||
| hppa | ||
| i386 | ||
| include | ||
| loongarch64 | ||
| m68k | ||
| microblaze | ||
| mips | ||
| mips64 | ||
| openrisc | ||
| ppc | ||
| riscv | ||
| s390x | ||
| sh4 | ||
| sparc | ||
| x86_64 | ||
| xtensa | ||
| elfload.c | ||
| errnos.c.inc | ||
| exit.c | ||
| fd-trans.c | ||
| fd-trans.h | ||
| flat.h | ||
| flatload.c | ||
| gen-vdso-elfn.c.inc | ||
| gen-vdso.c | ||
| ioctls.h | ||
| linux_loop.h | ||
| linuxload.c | ||
| loader.h | ||
| main.c | ||
| meson.build | ||
| mmap.c | ||
| qemu.h | ||
| semihost.c | ||
| signal-common.h | ||
| signal.c | ||
| socket.h | ||
| strace.c | ||
| strace.h | ||
| strace.list | ||
| syscall.c | ||
| syscall_defs.h | ||
| syscall_types.h | ||
| thunk.c | ||
| trace-events | ||
| trace.h | ||
| uaccess.c | ||
| uname.c | ||
| uname.h | ||
| user-internals.h | ||
| user-mmap.h | ||
| vm86.c | ||