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3037663616
Use the new delay_exceptionv function in the implementation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
36 lines
1.2 KiB
Text
36 lines
1.2 KiB
Text
# SPDX-License-Identifier: LGPL-2.0+
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#
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# Sparc instruction decode definitions.
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# Copyright (c) 2023 Richard Henderson <rth@twiddle.net>
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##
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## Major Opcodes 00 and 01 -- branches, call, and sethi.
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##
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&bcc i a cond cc
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BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc
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Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0
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FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc
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FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0
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%d16 20:s2 0:14
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BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16
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NCP 00 - ---- 111 ---------------------- # CBcc
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SETHI 00 rd:5 100 i:22
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CALL 01 i:s30
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Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
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{
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# For v7, the entire simm13 field is present, but masked to 7 bits.
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# For v8, [12:7] are reserved. However, a compatibility note for
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# the Tcc insn in the v9 manual suggests that the v8 reserved field
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# was ignored and did not produce traps.
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Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7
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# For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0).
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# Bits [10:8] are reserved and the OSA2011 manual says they must be 0.
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Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8
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}
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