Sunil V L faacd2e6b6 hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART ... The requirement ACPI_060 in the RISC-V BRS specification [1], requires NS16550 compatible UART to have the HID RSCV0003. So, update the HID for the UART. [1] - https://github.com/riscv-non-isa/riscv-brs/releases/download/v0.0.2/riscv-brs-spec.pdf (Chapter 6) Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240716144306.2432257-3-sunilvl@ventanamicro.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2024-07-22 20:15:42 -04:00
..
boot.c	hw/riscv/boot.c: Support 64-bit address for initrd	2024-06-03 11:12:11 +10:00
Kconfig	kconfig: express dependency of individual boards on libfdt	2024-05-10 15:45:15 +02:00
meson.build	meson: pick libfdt from common_ss when building target-specific files	2024-05-10 15:45:15 +02:00
microchip_pfsoc.c	hw/riscv: use qemu_configure_nic_device()	2024-02-02 16:23:47 +00:00
numa.c	hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix()	2024-02-09 20:43:14 +10:00
opentitan.c	hw/riscv: opentitan: Fixup local variables shadowing	2023-09-29 10:07:20 +02:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv/shakti_c: Check CPU type in machine_run_board_init()	2024-01-05 16:20:15 +01:00
sifive_e.c	riscv: Fix SiFive E CLINT clock frequency	2023-11-22 13:57:19 +10:00
sifive_u.c	target/riscv: support new isa extension detection devicetree properties	2024-02-09 20:43:14 +10:00
spike.c	target/riscv: support new isa extension detection devicetree properties	2024-02-09 20:43:14 +10:00
virt-acpi-build.c	hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART	2024-07-22 20:15:42 -04:00
virt.c	hw/riscv/virt.c: re-insert and deprecate 'riscv,delegate'	2024-07-18 12:08:45 +10:00