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6b8abd244b
For loongarch, mips, riscv and sparc, a zero register is available all the time. For aarch64, register index 31 depends on context: sometimes it is the stack pointer, and sometimes it is the zero register. Introduce a new general-purpose constraint which maps 0 to TCG_REG_ZERO, if defined. This differs from existing constant constraints in that const_arg[*] is recorded as false, indicating that the value is in a register. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
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| .. | ||
| debug-assert.h | ||
| debuginfo.h | ||
| helper-info.h | ||
| insn-start-words.h | ||
| perf.h | ||
| startup.h | ||
| tcg-cond.h | ||
| tcg-gvec-desc.h | ||
| tcg-ldst.h | ||
| tcg-mo.h | ||
| tcg-op-common.h | ||
| tcg-op-gvec-common.h | ||
| tcg-op-gvec.h | ||
| tcg-op.h | ||
| tcg-opc.h | ||
| tcg-temp-internal.h | ||
| tcg.h | ||