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The Write Protect pin of SDHCI model is default active low to match the SDHCI spec. So, write enable the bit 19 should be 1 and write protected the bit 19 should be 0 at the Present State Register (0x24). According to the design of AST2600 EVB, the Write Protected pin is active high by default. To support it, introduces a new "sdhci_wp_inverted" property in ASPEED MACHINE State and set it true for AST2600 EVB and set "wp_inverted" property true of sdhci-generic model. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20241114094839.4128404-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/*
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* Aspeed Machines
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*
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* Copyright 2018 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef ARM_ASPEED_H
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#define ARM_ASPEED_H
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#include "hw/boards.h"
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#include "qom/object.h"
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typedef struct AspeedMachineState AspeedMachineState;
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#define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed")
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typedef struct AspeedMachineClass AspeedMachineClass;
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DECLARE_OBJ_CHECKERS(AspeedMachineState, AspeedMachineClass,
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ASPEED_MACHINE, TYPE_ASPEED_MACHINE)
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#define ASPEED_MAC0_ON (1 << 0)
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#define ASPEED_MAC1_ON (1 << 1)
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#define ASPEED_MAC2_ON (1 << 2)
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#define ASPEED_MAC3_ON (1 << 3)
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struct AspeedMachineClass {
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MachineClass parent_obj;
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const char *name;
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const char *desc;
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const char *soc_name;
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uint32_t hw_strap1;
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uint32_t hw_strap2;
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const char *fmc_model;
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const char *spi_model;
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uint32_t num_cs;
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uint32_t macs_mask;
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void (*i2c_init)(AspeedMachineState *bmc);
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uint32_t uart_default;
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bool sdhci_wp_inverted;
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};
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#endif
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