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5c09d295e0
Include "cpu.h" earlier to get the MMU_USER_IDX definition soon
enough and avoid when refactoring unrelated headers:
In file included from include/exec/translator.h:271,
from ../../accel/tcg/translator.c:13:
include/exec/cpu-all.h: In function ‘cpu_mmu_index’:
include/exec/cpu-all.h:274:12: error: ‘MMU_USER_IDX’ undeclared (first use in this function)
274 | return MMU_USER_IDX;
| ^~~~~~~~~~~~
include/exec/cpu-all.h:274:12: note: each undeclared identifier is reported only once for each function it appears in
ninja: build stopped: subcommand failed.
We need to forward-declare cpu_mmu_index() to avoid on user emulation:
In file included from include/exec/cpu-all.h:263,
from include/exec/translator.h:271,
from ../../accel/tcg/translator.c:13:
../../target/sparc/cpu.h: In function ‘cpu_get_tb_cpu_state’:
../../target/sparc/cpu.h:757:13: error: implicit declaration of function ‘cpu_mmu_index’ [-Werror=implicit-function-declaration]
757 | flags = cpu_mmu_index(env_cpu(env), false);
| ^~~~~~~~~~~~~
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241218155202.71931-5-philmd@linaro.org>
281 lines
8.9 KiB
C
281 lines
8.9 KiB
C
/*
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* defines common to all virtual CPUs
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_ALL_H
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#define CPU_ALL_H
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#include "exec/page-protection.h"
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#include "exec/cpu-common.h"
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#include "exec/memory.h"
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#include "exec/tswap.h"
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#include "hw/core/cpu.h"
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/* some important defines:
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*
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* HOST_BIG_ENDIAN : whether the host cpu is big endian and
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* otherwise little endian.
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*
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* TARGET_BIG_ENDIAN : same for the target cpu
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*/
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#if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
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#define BSWAP_NEEDED
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#endif
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/* Target-endianness CPU memory access functions. These fit into the
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* {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
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*/
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#if TARGET_BIG_ENDIAN
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#define lduw_p(p) lduw_be_p(p)
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#define ldsw_p(p) ldsw_be_p(p)
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#define ldl_p(p) ldl_be_p(p)
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#define ldq_p(p) ldq_be_p(p)
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#define stw_p(p, v) stw_be_p(p, v)
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#define stl_p(p, v) stl_be_p(p, v)
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#define stq_p(p, v) stq_be_p(p, v)
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#define ldn_p(p, sz) ldn_be_p(p, sz)
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#define stn_p(p, sz, v) stn_be_p(p, sz, v)
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#else
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#define lduw_p(p) lduw_le_p(p)
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#define ldsw_p(p) ldsw_le_p(p)
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#define ldl_p(p) ldl_le_p(p)
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#define ldq_p(p) ldq_le_p(p)
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#define stw_p(p, v) stw_le_p(p, v)
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#define stl_p(p, v) stl_le_p(p, v)
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#define stq_p(p, v) stq_le_p(p, v)
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#define ldn_p(p, sz) ldn_le_p(p, sz)
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#define stn_p(p, sz, v) stn_le_p(p, sz, v)
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#endif
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/* MMU memory access macros */
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#if !defined(CONFIG_USER_ONLY)
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#include "exec/hwaddr.h"
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#define SUFFIX
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#define ARG1 as
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#define ARG1_DECL AddressSpace *as
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#define TARGET_ENDIANNESS
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#include "exec/memory_ldst.h.inc"
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#define SUFFIX _cached_slow
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#define ARG1 cache
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#define ARG1_DECL MemoryRegionCache *cache
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#define TARGET_ENDIANNESS
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#include "exec/memory_ldst.h.inc"
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static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
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{
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address_space_stl_notdirty(as, addr, val,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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#define SUFFIX
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#define ARG1 as
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#define ARG1_DECL AddressSpace *as
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#define TARGET_ENDIANNESS
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#include "exec/memory_ldst_phys.h.inc"
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/* Inline fast path for direct RAM access. */
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#define ENDIANNESS
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#include "exec/memory_ldst_cached.h.inc"
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#define SUFFIX _cached
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#define ARG1 cache
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#define ARG1_DECL MemoryRegionCache *cache
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#define TARGET_ENDIANNESS
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#include "exec/memory_ldst_phys.h.inc"
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#endif
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/* page related stuff */
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#include "exec/cpu-defs.h"
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#ifdef TARGET_PAGE_BITS_VARY
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# include "exec/page-vary.h"
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extern const TargetPageBits target_page;
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# ifdef CONFIG_DEBUG_TCG
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# define TARGET_PAGE_BITS ({ assert(target_page.decided); \
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target_page.bits; })
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# define TARGET_PAGE_MASK ({ assert(target_page.decided); \
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(target_long)target_page.mask; })
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# else
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# define TARGET_PAGE_BITS target_page.bits
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# define TARGET_PAGE_MASK ((target_long)target_page.mask)
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# endif
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# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
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#else
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# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
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# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
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# define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
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#endif
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#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
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CPUArchState *cpu_copy(CPUArchState *env);
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/* Flags for use in ENV->INTERRUPT_PENDING.
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The numbers assigned here are non-sequential in order to preserve
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binary compatibility with the vmstate dump. Bit 0 (0x0001) was
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previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
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the vmstate dump. */
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/* External hardware interrupt pending. This is typically used for
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interrupts from devices. */
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#define CPU_INTERRUPT_HARD 0x0002
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/* Exit the current TB. This is typically used when some system-level device
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makes some change to the memory mapping. E.g. the a20 line change. */
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#define CPU_INTERRUPT_EXITTB 0x0004
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/* Halt the CPU. */
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#define CPU_INTERRUPT_HALT 0x0020
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/* Debug event pending. */
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#define CPU_INTERRUPT_DEBUG 0x0080
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/* Reset signal. */
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#define CPU_INTERRUPT_RESET 0x0400
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/* Several target-specific external hardware interrupts. Each target/cpu.h
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should define proper names based on these defines. */
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#define CPU_INTERRUPT_TGT_EXT_0 0x0008
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#define CPU_INTERRUPT_TGT_EXT_1 0x0010
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#define CPU_INTERRUPT_TGT_EXT_2 0x0040
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#define CPU_INTERRUPT_TGT_EXT_3 0x0200
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#define CPU_INTERRUPT_TGT_EXT_4 0x1000
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/* Several target-specific internal interrupts. These differ from the
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preceding target-specific interrupts in that they are intended to
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originate from within the cpu itself, typically in response to some
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instruction being executed. These, therefore, are not masked while
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single-stepping within the debugger. */
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#define CPU_INTERRUPT_TGT_INT_0 0x0100
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#define CPU_INTERRUPT_TGT_INT_1 0x0800
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#define CPU_INTERRUPT_TGT_INT_2 0x2000
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/* First unused bit: 0x4000. */
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/* The set of all bits that should be masked when single-stepping. */
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#define CPU_INTERRUPT_SSTEP_MASK \
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(CPU_INTERRUPT_HARD \
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| CPU_INTERRUPT_TGT_EXT_0 \
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| CPU_INTERRUPT_TGT_EXT_1 \
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| CPU_INTERRUPT_TGT_EXT_2 \
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| CPU_INTERRUPT_TGT_EXT_3 \
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| CPU_INTERRUPT_TGT_EXT_4)
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#include "cpu.h"
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#ifdef CONFIG_USER_ONLY
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static inline int cpu_mmu_index(CPUState *cs, bool ifetch);
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/*
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* Allow some level of source compatibility with softmmu. We do not
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* support any of the more exotic features, so only invalid pages may
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* be signaled by probe_access_flags().
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*/
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#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
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#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2))
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#define TLB_WATCHPOINT 0
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static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
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{
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return MMU_USER_IDX;
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}
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#else
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/*
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* Flags stored in the low bits of the TLB virtual address.
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* These are defined so that fast path ram access is all zeros.
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* The flags all must be between TARGET_PAGE_BITS and
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* maximum address alignment bit.
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*
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* Use TARGET_PAGE_BITS_MIN so that these bits are constant
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* when TARGET_PAGE_BITS_VARY is in effect.
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*
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* The count, if not the placement of these bits is known
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* to tcg/tcg-op-ldst.c, check_max_alignment().
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*/
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/* Zero if TLB entry is valid. */
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#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
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/* Set if TLB entry references a clean RAM page. The iotlb entry will
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contain the page physical address. */
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#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
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/* Set if TLB entry is an IO callback. */
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#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
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/* Set if TLB entry writes ignored. */
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#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4))
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/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
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#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5))
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/*
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* Use this mask to check interception with an alignment mask
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* in a TCG backend.
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*/
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#define TLB_FLAGS_MASK \
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(TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
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| TLB_FORCE_SLOW | TLB_DISCARD_WRITE)
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/*
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* Flags stored in CPUTLBEntryFull.slow_flags[x].
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* TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x].
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*/
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/* Set if TLB entry requires byte swap. */
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#define TLB_BSWAP (1 << 0)
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/* Set if TLB entry contains a watchpoint. */
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#define TLB_WATCHPOINT (1 << 1)
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/* Set if TLB entry requires aligned accesses. */
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#define TLB_CHECK_ALIGNED (1 << 2)
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#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED)
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/* The two sets of flags must not overlap. */
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QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
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/**
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* tlb_hit_page: return true if page aligned @addr is a hit against the
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* TLB entry @tlb_addr
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*
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* @addr: virtual address to test (must be page aligned)
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* @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
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*/
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static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr)
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{
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return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
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}
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/**
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* tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
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*
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* @addr: virtual address to test (need not be page aligned)
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* @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
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*/
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static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr)
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{
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return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
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}
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#endif /* !CONFIG_USER_ONLY */
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/* Validate correct placement of CPUArchState. */
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QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
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QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
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#endif /* CPU_ALL_H */
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