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- Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander) - Add '-d invalid_mem' logging option (Zoltan) - Create QOM containers explicitly (Peter) - Rename sysemu/ -> system/ (Philippe) - Re-orderning of include/exec/ headers (Philippe) Move a lot of declarations from these legacy mixed bag headers: . "exec/cpu-all.h" . "exec/cpu-common.h" . "exec/cpu-defs.h" . "exec/exec-all.h" . "exec/translate-all" to these more specific ones: . "exec/page-protection.h" . "exec/translation-block.h" . "user/cpu_loop.h" . "user/guest-host.h" . "user/page-protection.h" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmdlnyAACgkQ4+MsLN6t wN6mBw//QFWi7CrU+bb8KMM53kOU9C507tjn99LLGFb5or73/umDsw6eo/b8DHBt KIwGLgATel42oojKfNKavtAzLK5rOrywpboPDpa3SNeF1onW+99NGJ52LQUqIX6K A6bS0fPdGG9ZzEuPpbjDXlp++0yhDcdSgZsS42fEsT7Dyj5gzJYlqpqhiXGqpsn8 4Y0UMxSL21K3HEexlzw2hsoOBFA3tUm2ujNDhNkt8QASr85yQVLCypABJnuoe/// 5Ojl5wTBeDwhANET0rhwHK8eIYaNboiM9fHopJYhvyw1bz6yAu9jQwzF/MrL3s/r xa4OBHBy5mq2hQV9Shcl3UfCQdk/vDaYaWpgzJGX8stgMGYfnfej1SIl8haJIfcl VMX8/jEFdYbjhO4AeGRYcBzWjEJymkDJZoiSWp2NuEDi6jqIW+7yW1q0Rnlg9lay ShAqLK5Pv4zUw3t0Jy3qv9KSW8sbs6PQxtzXjk8p97rTf76BJ2pF8sv1tVzmsidP 9L92Hv5O34IqzBu2oATOUZYJk89YGmTIUSLkpT7asJZpBLwNM2qLp5jO00WVU0Sd +kAn324guYPkko/TVnjC/AY7CMu55EOtD9NU35k3mUAnxXT9oDUeL4NlYtfgrJx6 x1Nzr2FkS68+wlPAFKNSSU5lTjsjNaFM0bIJ4LCNtenJVP+SnRo= =cjz8 -----END PGP SIGNATURE----- Merge tag 'exec-20241220' of https://github.com/philmd/qemu into staging Accel & Exec patch queue - Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander) - Add '-d invalid_mem' logging option (Zoltan) - Create QOM containers explicitly (Peter) - Rename sysemu/ -> system/ (Philippe) - Re-orderning of include/exec/ headers (Philippe) Move a lot of declarations from these legacy mixed bag headers: . "exec/cpu-all.h" . "exec/cpu-common.h" . "exec/cpu-defs.h" . "exec/exec-all.h" . "exec/translate-all" to these more specific ones: . "exec/page-protection.h" . "exec/translation-block.h" . "user/cpu_loop.h" . "user/guest-host.h" . "user/page-protection.h" # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmdlnyAACgkQ4+MsLN6t # wN6mBw//QFWi7CrU+bb8KMM53kOU9C507tjn99LLGFb5or73/umDsw6eo/b8DHBt # KIwGLgATel42oojKfNKavtAzLK5rOrywpboPDpa3SNeF1onW+99NGJ52LQUqIX6K # A6bS0fPdGG9ZzEuPpbjDXlp++0yhDcdSgZsS42fEsT7Dyj5gzJYlqpqhiXGqpsn8 # 4Y0UMxSL21K3HEexlzw2hsoOBFA3tUm2ujNDhNkt8QASr85yQVLCypABJnuoe/// # 5Ojl5wTBeDwhANET0rhwHK8eIYaNboiM9fHopJYhvyw1bz6yAu9jQwzF/MrL3s/r # xa4OBHBy5mq2hQV9Shcl3UfCQdk/vDaYaWpgzJGX8stgMGYfnfej1SIl8haJIfcl # VMX8/jEFdYbjhO4AeGRYcBzWjEJymkDJZoiSWp2NuEDi6jqIW+7yW1q0Rnlg9lay # ShAqLK5Pv4zUw3t0Jy3qv9KSW8sbs6PQxtzXjk8p97rTf76BJ2pF8sv1tVzmsidP # 9L92Hv5O34IqzBu2oATOUZYJk89YGmTIUSLkpT7asJZpBLwNM2qLp5jO00WVU0Sd # +kAn324guYPkko/TVnjC/AY7CMu55EOtD9NU35k3mUAnxXT9oDUeL4NlYtfgrJx6 # x1Nzr2FkS68+wlPAFKNSSU5lTjsjNaFM0bIJ4LCNtenJVP+SnRo= # =cjz8 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Dec 2024 11:45:20 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'exec-20241220' of https://github.com/philmd/qemu: (59 commits) util/qemu-timer: fix indentation meson: Do not define CONFIG_DEVICES on user emulation system/accel-ops: Remove unnecessary 'exec/cpu-common.h' header system/numa: Remove unnecessary 'exec/cpu-common.h' header hw/xen: Remove unnecessary 'exec/cpu-common.h' header target/mips: Drop left-over comment about Jazz machine target/mips: Remove tswap() calls in semihosting uhi_fstat_cb() target/xtensa: Remove tswap() calls in semihosting simcall() helper accel/tcg: Un-inline translator_is_same_page() accel/tcg: Include missing 'exec/translation-block.h' header accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h' accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h' qemu/coroutine: Include missing 'qemu/atomic.h' header exec/translation-block: Include missing 'qemu/atomic.h' header accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h' exec/cpu-all: Include 'cpu.h' earlier so MMU_USER_IDX is always defined target/sparc: Move sparc_restore_state_to_opc() to cpu.c target/sparc: Uninline cpu_get_tb_cpu_state() target/loongarch: Declare loongarch_cpu_dump_state() locally user: Move various declarations out of 'exec/exec-all.h' ... Conflicts: hw/char/riscv_htif.c hw/intc/riscv_aplic.c target/s390x/cpu.c Apply sysemu header path changes to not in the pull request. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
135 lines
3.7 KiB
C
135 lines
3.7 KiB
C
/*
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* QEMU simulated pvpanic device.
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*
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* Copyright Fujitsu, Corp. 2013
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*
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* Authors:
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* Wen Congyang <wency@cn.fujitsu.com>
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* Hu Tao <hutao@cn.fujitsu.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu/module.h"
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#include "system/runstate.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/qdev-properties.h"
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#include "hw/misc/pvpanic.h"
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#include "qom/object.h"
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#include "hw/isa/isa.h"
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#include "hw/acpi/acpi_aml_interface.h"
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OBJECT_DECLARE_SIMPLE_TYPE(PVPanicISAState, PVPANIC_ISA_DEVICE)
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/*
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* PVPanicISAState for ISA device and
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* use ioport.
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*/
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struct PVPanicISAState {
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ISADevice parent_obj;
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uint16_t ioport;
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PVPanicState pvpanic;
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};
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static void pvpanic_isa_initfn(Object *obj)
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{
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PVPanicISAState *s = PVPANIC_ISA_DEVICE(obj);
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pvpanic_setup_io(&s->pvpanic, DEVICE(s), 1);
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}
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static void pvpanic_isa_realizefn(DeviceState *dev, Error **errp)
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{
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ISADevice *d = ISA_DEVICE(dev);
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PVPanicISAState *s = PVPANIC_ISA_DEVICE(dev);
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PVPanicState *ps = &s->pvpanic;
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FWCfgState *fw_cfg = fw_cfg_find();
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uint16_t *pvpanic_port;
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if (!fw_cfg) {
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return;
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}
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pvpanic_port = g_malloc(sizeof(*pvpanic_port));
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*pvpanic_port = cpu_to_le16(s->ioport);
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fw_cfg_add_file(fw_cfg, "etc/pvpanic-port", pvpanic_port,
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sizeof(*pvpanic_port));
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isa_register_ioport(d, &ps->mr, s->ioport);
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}
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static void build_pvpanic_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
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{
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Aml *crs, *field, *method;
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PVPanicISAState *s = PVPANIC_ISA_DEVICE(adev);
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Aml *dev = aml_device("PEVT");
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aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
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crs = aml_resource_template();
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aml_append(crs,
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aml_io(AML_DECODE16, s->ioport, s->ioport, 1, 1)
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);
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aml_append(dev, aml_name_decl("_CRS", crs));
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aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
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aml_int(s->ioport), 1));
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field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
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aml_append(field, aml_named_field("PEPT", 8));
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aml_append(dev, field);
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/* device present, functioning, decoding, shown in UI */
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aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
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method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
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aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
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aml_append(method, aml_return(aml_local(0)));
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aml_append(dev, method);
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method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
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aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
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aml_append(dev, method);
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aml_append(scope, dev);
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}
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static const Property pvpanic_isa_properties[] = {
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DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicISAState, ioport, 0x505),
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DEFINE_PROP_UINT8("events", PVPanicISAState, pvpanic.events,
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PVPANIC_EVENTS),
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};
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static void pvpanic_isa_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
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dc->realize = pvpanic_isa_realizefn;
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device_class_set_props(dc, pvpanic_isa_properties);
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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adevc->build_dev_aml = build_pvpanic_isa_aml;
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}
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static const TypeInfo pvpanic_isa_info = {
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.name = TYPE_PVPANIC_ISA_DEVICE,
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(PVPanicISAState),
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.instance_init = pvpanic_isa_initfn,
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.class_init = pvpanic_isa_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_ACPI_DEV_AML_IF },
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{ },
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},
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};
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static void pvpanic_register_types(void)
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{
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type_register_static(&pvpanic_isa_info);
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}
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type_init(pvpanic_register_types)
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