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- Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander) - Add '-d invalid_mem' logging option (Zoltan) - Create QOM containers explicitly (Peter) - Rename sysemu/ -> system/ (Philippe) - Re-orderning of include/exec/ headers (Philippe) Move a lot of declarations from these legacy mixed bag headers: . "exec/cpu-all.h" . "exec/cpu-common.h" . "exec/cpu-defs.h" . "exec/exec-all.h" . "exec/translate-all" to these more specific ones: . "exec/page-protection.h" . "exec/translation-block.h" . "user/cpu_loop.h" . "user/guest-host.h" . "user/page-protection.h" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmdlnyAACgkQ4+MsLN6t wN6mBw//QFWi7CrU+bb8KMM53kOU9C507tjn99LLGFb5or73/umDsw6eo/b8DHBt KIwGLgATel42oojKfNKavtAzLK5rOrywpboPDpa3SNeF1onW+99NGJ52LQUqIX6K A6bS0fPdGG9ZzEuPpbjDXlp++0yhDcdSgZsS42fEsT7Dyj5gzJYlqpqhiXGqpsn8 4Y0UMxSL21K3HEexlzw2hsoOBFA3tUm2ujNDhNkt8QASr85yQVLCypABJnuoe/// 5Ojl5wTBeDwhANET0rhwHK8eIYaNboiM9fHopJYhvyw1bz6yAu9jQwzF/MrL3s/r xa4OBHBy5mq2hQV9Shcl3UfCQdk/vDaYaWpgzJGX8stgMGYfnfej1SIl8haJIfcl VMX8/jEFdYbjhO4AeGRYcBzWjEJymkDJZoiSWp2NuEDi6jqIW+7yW1q0Rnlg9lay ShAqLK5Pv4zUw3t0Jy3qv9KSW8sbs6PQxtzXjk8p97rTf76BJ2pF8sv1tVzmsidP 9L92Hv5O34IqzBu2oATOUZYJk89YGmTIUSLkpT7asJZpBLwNM2qLp5jO00WVU0Sd +kAn324guYPkko/TVnjC/AY7CMu55EOtD9NU35k3mUAnxXT9oDUeL4NlYtfgrJx6 x1Nzr2FkS68+wlPAFKNSSU5lTjsjNaFM0bIJ4LCNtenJVP+SnRo= =cjz8 -----END PGP SIGNATURE----- Merge tag 'exec-20241220' of https://github.com/philmd/qemu into staging Accel & Exec patch queue - Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander) - Add '-d invalid_mem' logging option (Zoltan) - Create QOM containers explicitly (Peter) - Rename sysemu/ -> system/ (Philippe) - Re-orderning of include/exec/ headers (Philippe) Move a lot of declarations from these legacy mixed bag headers: . "exec/cpu-all.h" . "exec/cpu-common.h" . "exec/cpu-defs.h" . "exec/exec-all.h" . "exec/translate-all" to these more specific ones: . "exec/page-protection.h" . "exec/translation-block.h" . "user/cpu_loop.h" . "user/guest-host.h" . "user/page-protection.h" # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmdlnyAACgkQ4+MsLN6t # wN6mBw//QFWi7CrU+bb8KMM53kOU9C507tjn99LLGFb5or73/umDsw6eo/b8DHBt # KIwGLgATel42oojKfNKavtAzLK5rOrywpboPDpa3SNeF1onW+99NGJ52LQUqIX6K # A6bS0fPdGG9ZzEuPpbjDXlp++0yhDcdSgZsS42fEsT7Dyj5gzJYlqpqhiXGqpsn8 # 4Y0UMxSL21K3HEexlzw2hsoOBFA3tUm2ujNDhNkt8QASr85yQVLCypABJnuoe/// # 5Ojl5wTBeDwhANET0rhwHK8eIYaNboiM9fHopJYhvyw1bz6yAu9jQwzF/MrL3s/r # xa4OBHBy5mq2hQV9Shcl3UfCQdk/vDaYaWpgzJGX8stgMGYfnfej1SIl8haJIfcl # VMX8/jEFdYbjhO4AeGRYcBzWjEJymkDJZoiSWp2NuEDi6jqIW+7yW1q0Rnlg9lay # ShAqLK5Pv4zUw3t0Jy3qv9KSW8sbs6PQxtzXjk8p97rTf76BJ2pF8sv1tVzmsidP # 9L92Hv5O34IqzBu2oATOUZYJk89YGmTIUSLkpT7asJZpBLwNM2qLp5jO00WVU0Sd # +kAn324guYPkko/TVnjC/AY7CMu55EOtD9NU35k3mUAnxXT9oDUeL4NlYtfgrJx6 # x1Nzr2FkS68+wlPAFKNSSU5lTjsjNaFM0bIJ4LCNtenJVP+SnRo= # =cjz8 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Dec 2024 11:45:20 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'exec-20241220' of https://github.com/philmd/qemu: (59 commits) util/qemu-timer: fix indentation meson: Do not define CONFIG_DEVICES on user emulation system/accel-ops: Remove unnecessary 'exec/cpu-common.h' header system/numa: Remove unnecessary 'exec/cpu-common.h' header hw/xen: Remove unnecessary 'exec/cpu-common.h' header target/mips: Drop left-over comment about Jazz machine target/mips: Remove tswap() calls in semihosting uhi_fstat_cb() target/xtensa: Remove tswap() calls in semihosting simcall() helper accel/tcg: Un-inline translator_is_same_page() accel/tcg: Include missing 'exec/translation-block.h' header accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h' accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h' qemu/coroutine: Include missing 'qemu/atomic.h' header exec/translation-block: Include missing 'qemu/atomic.h' header accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h' exec/cpu-all: Include 'cpu.h' earlier so MMU_USER_IDX is always defined target/sparc: Move sparc_restore_state_to_opc() to cpu.c target/sparc: Uninline cpu_get_tb_cpu_state() target/loongarch: Declare loongarch_cpu_dump_state() locally user: Move various declarations out of 'exec/exec-all.h' ... Conflicts: hw/char/riscv_htif.c hw/intc/riscv_aplic.c target/s390x/cpu.c Apply sysemu header path changes to not in the pull request. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
197 lines
6.6 KiB
C
197 lines
6.6 KiB
C
/*
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* Coherent Processing System emulation.
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*
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* Copyright (c) 2016 Imagination Technologies
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/mips/cps.h"
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#include "hw/mips/mips.h"
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#include "hw/qdev-clock.h"
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#include "hw/qdev-properties.h"
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#include "system/kvm.h"
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#include "system/reset.h"
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qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
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{
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assert(pin_number < s->num_irq);
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return s->gic.irq_state[pin_number].irq;
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}
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static void mips_cps_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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MIPSCPSState *s = MIPS_CPS(obj);
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s->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL, 0);
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/*
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* Cover entire address space as there do not seem to be any
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* constraints for the base address of CPC and GIC.
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*/
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memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
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sysbus_init_mmio(sbd, &s->container);
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}
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static void main_cpu_reset(void *opaque)
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{
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MIPSCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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cpu_reset(cs);
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}
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static bool cpu_mips_itu_supported(CPUMIPSState *env)
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{
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bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env);
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return is_mt && !kvm_enabled();
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}
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static void mips_cps_realize(DeviceState *dev, Error **errp)
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{
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MIPSCPSState *s = MIPS_CPS(dev);
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target_ulong gcr_base;
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bool itu_present = false;
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if (!clock_get(s->clock)) {
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error_setg(errp, "CPS input clock is not connected to an output clock");
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return;
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}
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for (int i = 0; i < s->num_vp; i++) {
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MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type));
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CPUMIPSState *env = &cpu->env;
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object_property_set_bool(OBJECT(cpu), "big-endian", s->cpu_is_bigendian,
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&error_abort);
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/* All VPs are halted on reset. Leave powering up to CPC. */
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object_property_set_bool(OBJECT(cpu), "start-powered-off", true,
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&error_abort);
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/* All cores use the same clock tree */
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qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock);
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if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) {
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return;
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}
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/* Init internal devices */
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cpu_mips_irq_init_cpu(cpu);
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cpu_mips_clock_init(cpu);
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if (cpu_mips_itu_supported(env)) {
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itu_present = true;
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/* Attach ITC Tag to the VP */
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env->itc_tag = mips_itu_get_tag_region(&s->itu);
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}
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qemu_register_reset(main_cpu_reset, cpu);
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}
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/* Inter-Thread Communication Unit */
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if (itu_present) {
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object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU);
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object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16,
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&error_abort);
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object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16,
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) {
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return;
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}
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
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}
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/* Cluster Power Controller */
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object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC);
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object_property_set_uint(OBJECT(&s->cpc), "num-vp", s->num_vp,
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&error_abort);
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object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1,
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) {
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return;
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}
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
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/* Global Interrupt Controller */
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object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC);
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object_property_set_uint(OBJECT(&s->gic), "num-vp", s->num_vp,
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&error_abort);
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object_property_set_uint(OBJECT(&s->gic), "num-irq", 128,
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
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return;
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}
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
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/* Global Configuration Registers */
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gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4;
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object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR);
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object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp,
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&error_abort);
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object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800,
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&error_abort);
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object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base,
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&error_abort);
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object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr),
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&error_abort);
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object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
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return;
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}
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memory_region_add_subregion(&s->container, gcr_base,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
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}
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static const Property mips_cps_properties[] = {
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DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
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DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
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DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
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DEFINE_PROP_BOOL("cpu-big-endian", MIPSCPSState, cpu_is_bigendian, false),
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};
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static void mips_cps_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = mips_cps_realize;
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device_class_set_props(dc, mips_cps_properties);
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}
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static const TypeInfo mips_cps_info = {
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.name = TYPE_MIPS_CPS,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MIPSCPSState),
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.instance_init = mips_cps_init,
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.class_init = mips_cps_class_init,
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};
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static void mips_cps_register_types(void)
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{
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type_register_static(&mips_cps_info);
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}
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type_init(mips_cps_register_types)
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