Julia Suvorova 2aeba0d007 target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline ... Unlike ARMv7-M, ARMv6-M and ARMv8-M Baseline only supports naturally aligned memory accesses for load/store instructions. Signed-off-by: Julia Suvorova <jusual@mail.ru> Message-id: 20180622080138.17702-3-jusual@mail.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2018-06-22 13:28:41 +01:00
..
alpha	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-01 15:15:27 -07:00
arm	target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline	2018-06-22 13:28:41 +01:00
cris	tcg-next queue	2018-06-04 11:28:31 +01:00
hppa	tcg-next queue	2018-06-04 11:28:31 +01:00
i386	i386: Populate AMD Processor Cache Information for cpuid 0x8000001D	2018-06-08 15:54:10 -03:00
lm32	tcg-next queue	2018-06-04 11:28:31 +01:00
m68k	target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn	2018-06-11 12:43:42 +02:00
microblaze	target-microblaze: Rework NOP/zero instruction handling	2018-06-15 09:05:00 +02:00
mips	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-01 15:15:27 -07:00
moxie	tcg-next queue	2018-06-04 11:28:31 +01:00
nios2	tcg-next queue	2018-06-04 11:28:31 +01:00
openrisc	tcg-next queue	2018-06-04 11:28:31 +01:00
ppc	target/ppc, spapr: Move VPA information to machine_data	2018-06-16 16:32:50 +10:00
riscv	RISC-V: Add trailing '\n' to qemu_log() calls	2018-06-08 13:15:33 +01:00
s390x	s390x/cpumodels: add z14 Model ZR1	2018-06-18 10:50:32 +02:00
sh4	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-01 15:15:27 -07:00
sparc	SPARC64: add icount support	2018-06-17 11:13:06 +01:00
tilegx	tcg-next queue	2018-06-04 11:28:31 +01:00
tricore	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-01 15:15:27 -07:00
unicore32	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-01 15:15:27 -07:00
xtensa	target/xtensa: Add trailing '\n' to qemu_log() calls	2018-06-08 13:15:33 +01:00