mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-02 15:23:53 -06:00
2a8756ed7d
The RISC-V device-tree code has a number of hard-coded constants and this change moves them into header enums. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
/*
|
|
* Spike machine interface
|
|
*
|
|
* Copyright (c) 2017 SiFive, Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2 or later, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along with
|
|
* this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#ifndef HW_SPIKE_H
|
|
#define HW_SPIKE_H
|
|
|
|
#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1"
|
|
#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10"
|
|
|
|
#define SPIKE(obj) \
|
|
OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD)
|
|
|
|
typedef struct {
|
|
/*< private >*/
|
|
SysBusDevice parent_obj;
|
|
|
|
/*< public >*/
|
|
RISCVHartArrayState soc;
|
|
void *fdt;
|
|
int fdt_size;
|
|
} SpikeState;
|
|
|
|
|
|
enum {
|
|
SPIKE_MROM,
|
|
SPIKE_CLINT,
|
|
SPIKE_DRAM
|
|
};
|
|
|
|
enum {
|
|
SPIKE_CLOCK_FREQ = 1000000000
|
|
};
|
|
|
|
#if defined(TARGET_RISCV32)
|
|
#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
|
|
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
|
|
#elif defined(TARGET_RISCV64)
|
|
#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
|
|
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
|
|
#endif
|
|
|
|
#endif
|