Tommy Wu 3157a553ec target/riscv: Add Smrnmi mnret instruction ... This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang <frank.chang@sifive.com> Signed-off-by: Tommy Wu <tommy.wu@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250106054336.1878291-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2025-01-19 09:44:34 +10:00
..
trans_privileged.c.inc	target/riscv: Add Smrnmi mnret instruction	2025-01-19 09:44:34 +10:00
trans_rva.c.inc	target/riscv: update decode_save_opc to store extra word2	2024-10-30 11:22:08 +10:00
trans_rvb.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_rvbf16.c.inc	target/riscv: enable 'vstart_eq_zero' in the end of insns	2024-03-22 15:24:37 +10:00
trans_rvd.c.inc	target/riscv: update decode_save_opc to store extra word2	2024-10-30 11:22:08 +10:00
trans_rvf.c.inc	target/riscv: update decode_save_opc to store extra word2	2024-10-30 11:22:08 +10:00
trans_rvh.c.inc	target/riscv: update decode_save_opc to store extra word2	2024-10-30 11:22:08 +10:00
trans_rvi.c.inc	target/riscv: update decode_save_opc to store extra word2	2024-10-30 11:22:08 +10:00
trans_rvk.c.inc	target/riscv: Drop tcg_temp_free	2023-03-05 13:44:08 -08:00
trans_rvm.c.inc	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
trans_rvv.c.inc	target/riscv: Set vdata.vm field for vector load/store whole register instructions	2024-11-07 08:21:14 +10:00
trans_rvvk.c.inc	target/riscv: update decode_save_opc to store extra word2	2024-10-30 11:22:08 +10:00
trans_rvzabha.c.inc	target/riscv: Add amocas.[b|h] for Zabha	2024-07-18 12:00:42 +10:00
trans_rvzacas.c.inc	target/riscv: update decode_save_opc to store extra word2	2024-10-30 11:22:08 +10:00
trans_rvzawrs.c.inc	target/riscv: Raise exceptions on wrs.nto	2024-06-03 11:12:11 +10:00
trans_rvzce.c.inc	target/riscv: Update $ra with current $pc in trans_cm_jalt()	2024-03-08 15:37:20 +10:00
trans_rvzcmop.c.inc	target/riscv: Add zcmop extension	2024-07-18 12:00:42 +10:00
trans_rvzfa.c.inc	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
trans_rvzfh.c.inc	target/riscv: update decode_save_opc to store extra word2	2024-10-30 11:22:08 +10:00
trans_rvzicbo.c.inc	target/riscv: rvzicbo: Fixup CBO extension register calculation	2024-06-03 11:12:12 +10:00
trans_rvzicfiss.c.inc	target/riscv: implement zicfiss instructions	2024-10-30 11:22:08 +10:00
trans_rvzicond.c.inc	target/riscv: refactor Zicond support	2023-05-05 10:49:50 +10:00
trans_rvzimop.c.inc	target/riscv: Add zimop extension	2024-07-18 12:00:42 +10:00
trans_svinval.c.inc	target/riscv: update decode_save_opc to store extra word2	2024-10-30 11:22:08 +10:00
trans_xthead.c.inc	target/riscv: Enable xtheadsync under user mode	2024-02-09 20:43:14 +10:00
trans_xventanacondops.c.inc	target/riscv: redirect XVentanaCondOps to use the Zicond functions	2023-05-05 10:49:50 +10:00