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29abd3d112
This implementation provides emulation for the Xiangshan Kunminghu FPGA prototype platform, including support for UART, CLINT, IMSIC, and APLIC devices. More details can be found at https://github.com/OpenXiangShan/XiangShan Signed-off-by: qinshaoqing <qinshaoqing@bosc.ac.cn> Signed-off-by: Yang Wang <wangyang@bosc.ac.cn> Signed-off-by: Yu Hu <819258943@qq.com> Signed-off-by: Ran Wang <wangran@bosc.ac.cn> Signed-off-by: Borong Huang <3543977024@qq.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250617074222.17618-1-wangran@bosc.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
220 lines
8 KiB
C
220 lines
8 KiB
C
/*
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* QEMU RISC-V Board Compatible with the Xiangshan Kunminghu
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* FPGA prototype platform
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*
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* Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC)
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Provides a board compatible with the Xiangshan Kunminghu
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* FPGA prototype platform:
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*
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* 0) UART (16550A)
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* 1) CLINT (Core-Local Interruptor)
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* 2) IMSIC (Incoming MSI Controller)
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* 3) APLIC (Advanced Platform-Level Interrupt Controller)
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*
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* More information can be found in our Github repository:
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* https://github.com/OpenXiangShan/XiangShan
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "system/address-spaces.h"
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#include "hw/boards.h"
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#include "hw/char/serial-mm.h"
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#include "hw/intc/riscv_aclint.h"
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#include "hw/intc/riscv_aplic.h"
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#include "hw/intc/riscv_imsic.h"
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#include "hw/qdev-properties.h"
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#include "hw/riscv/boot.h"
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#include "hw/riscv/xiangshan_kmh.h"
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#include "hw/riscv/riscv_hart.h"
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#include "system/system.h"
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static const MemMapEntry xiangshan_kmh_memmap[] = {
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[XIANGSHAN_KMH_ROM] = { 0x1000, 0xF000 },
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[XIANGSHAN_KMH_UART0] = { 0x310B0000, 0x10000 },
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[XIANGSHAN_KMH_CLINT] = { 0x38000000, 0x10000 },
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[XIANGSHAN_KMH_APLIC_M] = { 0x31100000, 0x4000 },
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[XIANGSHAN_KMH_APLIC_S] = { 0x31120000, 0x4000 },
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[XIANGSHAN_KMH_IMSIC_M] = { 0x3A800000, 0x10000 },
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[XIANGSHAN_KMH_IMSIC_S] = { 0x3B000000, 0x80000 },
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[XIANGSHAN_KMH_DRAM] = { 0x80000000, 0x0 },
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};
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static DeviceState *xiangshan_kmh_create_aia(uint32_t num_harts)
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{
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int i;
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const MemMapEntry *memmap = xiangshan_kmh_memmap;
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hwaddr addr = 0;
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DeviceState *aplic_m = NULL;
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/* M-level IMSICs */
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addr = memmap[XIANGSHAN_KMH_IMSIC_M].base;
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for (i = 0; i < num_harts; i++) {
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riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), i, true,
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1, XIANGSHAN_KMH_IMSIC_NUM_IDS);
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}
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/* S-level IMSICs */
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addr = memmap[XIANGSHAN_KMH_IMSIC_S].base;
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for (i = 0; i < num_harts; i++) {
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riscv_imsic_create(addr +
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i * IMSIC_HART_SIZE(XIANGSHAN_KMH_IMSIC_GUEST_BITS),
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i, false, 1 + XIANGSHAN_KMH_IMSIC_GUEST_BITS,
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XIANGSHAN_KMH_IMSIC_NUM_IDS);
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}
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/* M-level APLIC */
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aplic_m = riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_M].base,
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memmap[XIANGSHAN_KMH_APLIC_M].size,
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0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES,
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1, true, true, NULL);
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/* S-level APLIC */
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riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_S].base,
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memmap[XIANGSHAN_KMH_APLIC_S].size,
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0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES,
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1, true, false, aplic_m);
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return aplic_m;
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}
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static void xiangshan_kmh_soc_realize(DeviceState *dev, Error **errp)
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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XiangshanKmhSoCState *s = XIANGSHAN_KMH_SOC(dev);
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const MemMapEntry *memmap = xiangshan_kmh_memmap;
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MemoryRegion *system_memory = get_system_memory();
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uint32_t num_harts = ms->smp.cpus;
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qdev_prop_set_uint32(DEVICE(&s->cpus), "num-harts", num_harts);
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qdev_prop_set_uint32(DEVICE(&s->cpus), "hartid-base", 0);
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qdev_prop_set_string(DEVICE(&s->cpus), "cpu-type",
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TYPE_RISCV_CPU_XIANGSHAN_KMH);
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sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
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/* AIA */
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s->irqchip = xiangshan_kmh_create_aia(num_harts);
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/* UART */
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serial_mm_init(system_memory, memmap[XIANGSHAN_KMH_UART0].base, 2,
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qdev_get_gpio_in(s->irqchip, XIANGSHAN_KMH_UART0_IRQ),
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115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
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/* CLINT */
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riscv_aclint_swi_create(memmap[XIANGSHAN_KMH_CLINT].base,
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0, num_harts, false);
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riscv_aclint_mtimer_create(memmap[XIANGSHAN_KMH_CLINT].base +
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RISCV_ACLINT_SWI_SIZE,
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RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
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0, num_harts, RISCV_ACLINT_DEFAULT_MTIMECMP,
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RISCV_ACLINT_DEFAULT_MTIME,
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XIANGSHAN_KMH_CLINT_TIMEBASE_FREQ, true);
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/* ROM */
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memory_region_init_rom(&s->rom, OBJECT(dev), "xiangshan.kunminghu.rom",
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memmap[XIANGSHAN_KMH_ROM].size, &error_fatal);
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memory_region_add_subregion(system_memory,
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memmap[XIANGSHAN_KMH_ROM].base, &s->rom);
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}
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static void xiangshan_kmh_soc_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = xiangshan_kmh_soc_realize;
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dc->user_creatable = false;
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}
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static void xiangshan_kmh_soc_instance_init(Object *obj)
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{
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XiangshanKmhSoCState *s = XIANGSHAN_KMH_SOC(obj);
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object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
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}
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static const TypeInfo xiangshan_kmh_soc_info = {
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.name = TYPE_XIANGSHAN_KMH_SOC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(XiangshanKmhSoCState),
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.instance_init = xiangshan_kmh_soc_instance_init,
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.class_init = xiangshan_kmh_soc_class_init,
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};
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static void xiangshan_kmh_soc_register_types(void)
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{
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type_register_static(&xiangshan_kmh_soc_info);
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}
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type_init(xiangshan_kmh_soc_register_types)
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static void xiangshan_kmh_machine_init(MachineState *machine)
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{
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XiangshanKmhState *s = XIANGSHAN_KMH_MACHINE(machine);
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const MemMapEntry *memmap = xiangshan_kmh_memmap;
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MemoryRegion *system_memory = get_system_memory();
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hwaddr start_addr = memmap[XIANGSHAN_KMH_DRAM].base;
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/* Initialize SoC */
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object_initialize_child(OBJECT(machine), "soc", &s->soc,
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TYPE_XIANGSHAN_KMH_SOC);
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qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
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/* Register RAM */
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memory_region_add_subregion(system_memory,
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memmap[XIANGSHAN_KMH_DRAM].base,
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machine->ram);
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/* ROM reset vector */
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riscv_setup_rom_reset_vec(machine, &s->soc.cpus,
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start_addr,
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memmap[XIANGSHAN_KMH_ROM].base,
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memmap[XIANGSHAN_KMH_ROM].size, 0, 0);
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if (machine->firmware) {
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riscv_load_firmware(machine->firmware, &start_addr, NULL);
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}
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/* Note: dtb has been integrated into firmware(OpenSBI) when compiling */
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}
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static void xiangshan_kmh_machine_class_init(ObjectClass *klass, const void *data)
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{
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MachineClass *mc = MACHINE_CLASS(klass);
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static const char *const valid_cpu_types[] = {
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TYPE_RISCV_CPU_XIANGSHAN_KMH,
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NULL
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};
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mc->desc = "RISC-V Board compatible with the Xiangshan " \
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"Kunminghu FPGA prototype platform";
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mc->init = xiangshan_kmh_machine_init;
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mc->max_cpus = XIANGSHAN_KMH_MAX_CPUS;
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mc->default_cpu_type = TYPE_RISCV_CPU_XIANGSHAN_KMH;
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mc->valid_cpu_types = valid_cpu_types;
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mc->default_ram_id = "xiangshan.kunminghu.ram";
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}
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static const TypeInfo xiangshan_kmh_machine_info = {
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.name = TYPE_XIANGSHAN_KMH_MACHINE,
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.parent = TYPE_MACHINE,
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.instance_size = sizeof(XiangshanKmhState),
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.class_init = xiangshan_kmh_machine_class_init,
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};
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static void xiangshan_kmh_machine_register_types(void)
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{
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type_register_static(&xiangshan_kmh_machine_info);
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}
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type_init(xiangshan_kmh_machine_register_types)
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