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https://github.com/Motorhead1991/qemu.git
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29abd3d112
This implementation provides emulation for the Xiangshan Kunminghu FPGA prototype platform, including support for UART, CLINT, IMSIC, and APLIC devices. More details can be found at https://github.com/OpenXiangShan/XiangShan Signed-off-by: qinshaoqing <qinshaoqing@bosc.ac.cn> Signed-off-by: Yang Wang <wangyang@bosc.ac.cn> Signed-off-by: Yu Hu <819258943@qq.com> Signed-off-by: Ran Wang <wangran@bosc.ac.cn> Signed-off-by: Borong Huang <3543977024@qq.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250617074222.17618-1-wangran@bosc.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
130 lines
2.4 KiB
Text
130 lines
2.4 KiB
Text
config RISCV_IOMMU
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bool
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config RISCV_NUMA
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bool
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config IBEX
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bool
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# RISC-V machines in alphabetical order
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config MICROCHIP_PFSOC
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bool
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default y
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depends on RISCV64
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select CADENCE_SDHCI
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select CPU_CLUSTER
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select DEVICE_TREE
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select MCHP_PFSOC_DMC
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select MCHP_PFSOC_IOSCB
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select MCHP_PFSOC_MMUART
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select MCHP_PFSOC_SYSREG
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select RISCV_ACLINT
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select SIFIVE_PDMA
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select SIFIVE_PLIC
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select UNIMP
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config MICROBLAZE_V
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bool
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default y
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depends on RISCV32 || RISCV64
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select XILINX
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select XILINX_AXI
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select XILINX_ETHLITE
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config OPENTITAN
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bool
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default y
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depends on RISCV32
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select IBEX
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select SIFIVE_PLIC
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select UNIMP
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config RISCV_VIRT
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bool
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default y
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depends on RISCV32 || RISCV64
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imply PCI_DEVICES
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imply VIRTIO_VGA
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imply TEST_DEVICES
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imply TPM_TIS_SYSBUS
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select DEVICE_TREE
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select RISCV_NUMA
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select GOLDFISH_RTC
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select PCI
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select PCI_EXPRESS_GENERIC_BRIDGE
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select PFLASH_CFI01
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select SERIAL_MM
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select RISCV_ACLINT
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select RISCV_APLIC
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select RISCV_IOMMU
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select RISCV_IMSIC
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select SIFIVE_PLIC
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select SIFIVE_TEST
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select SMBIOS
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select VIRTIO_MMIO
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select FW_CFG_DMA
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select PLATFORM_BUS
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select ACPI
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select ACPI_PCI
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config SHAKTI_C
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bool
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default y
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depends on RISCV64
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select RISCV_ACLINT
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select SHAKTI_UART
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select SIFIVE_PLIC
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select UNIMP
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config SIFIVE_E
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bool
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default y
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depends on RISCV32 || RISCV64
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select RISCV_ACLINT
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select SIFIVE_GPIO
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select SIFIVE_PLIC
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select SIFIVE_UART
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select SIFIVE_E_PRCI
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select SIFIVE_E_AON
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select UNIMP
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config SIFIVE_U
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bool
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default y
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depends on RISCV32 || RISCV64
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select CADENCE
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select CPU_CLUSTER
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select DEVICE_TREE
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select RISCV_ACLINT
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select SIFIVE_GPIO
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select SIFIVE_PDMA
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select SIFIVE_PLIC
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select SIFIVE_SPI
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select SIFIVE_UART
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select SIFIVE_U_OTP
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select SIFIVE_U_PRCI
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select SIFIVE_PWM
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select SSI_M25P80
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select SSI_SD
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select UNIMP
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config SPIKE
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bool
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default y
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depends on RISCV32 || RISCV64
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select DEVICE_TREE
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select RISCV_NUMA
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select HTIF
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select RISCV_ACLINT
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select SIFIVE_PLIC
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config XIANGSHAN_KUNMINGHU
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bool
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default y
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depends on RISCV64
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select RISCV_ACLINT
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select RISCV_APLIC
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select RISCV_IMSIC
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select SERIAL_MM
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