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SPI controller device model supports a connection to a single SPI responder. This provide access to SPI seeproms, TPM, flash device and an ADC controller. All SPI function control is mapped into the SPI register space to enable full control by firmware. In this commit SPI configuration component is modelled which contains all SPI configuration and status registers as well as the hold registers for data to be sent or having been received. An existing QEMU SSI framework is used and SSI_BUS is created. Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> [np: Fix FDT macro compile for qtest] Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
40 lines
920 B
C
40 lines
920 B
C
/*
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* QEMU PowerPC SPI model
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*
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* Copyright (c) 2024, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This model Supports a connection to a single SPI responder.
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* Introduced for P10 to provide access to SPI seeproms, TPM, flash device
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* and an ADC controller.
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*/
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#ifndef PPC_PNV_SPI_H
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#define PPC_PNV_SPI_H
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#include "hw/ssi/ssi.h"
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#include "hw/sysbus.h"
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#define TYPE_PNV_SPI "pnv-spi"
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OBJECT_DECLARE_SIMPLE_TYPE(PnvSpi, PNV_SPI)
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#define PNV_SPI_REG_SIZE 8
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#define PNV_SPI_REGS 7
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#define TYPE_PNV_SPI_BUS "pnv-spi-bus"
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typedef struct PnvSpi {
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SysBusDevice parent_obj;
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SSIBus *ssi_bus;
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qemu_irq *cs_line;
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MemoryRegion xscom_spic_regs;
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/* SPI object number */
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uint32_t spic_num;
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/* SPI registers */
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uint64_t regs[PNV_SPI_REGS];
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uint8_t seq_op[PNV_SPI_REG_SIZE];
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uint64_t status;
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} PnvSpi;
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#endif /* PPC_PNV_SPI_H */
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