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2215e297b9
The interrupt level should be 0 or 1. The existing code was using the interrupt flags to determine the level. In the only machine currently supported (xlnx-versal-virt), the GICv3 was masking off all bits except bit 0 when applying it, resulting in the IRQ never being delivered. Signed-off-by: Doug Brown <doug@schmorgal.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Message-id: 20240827034927.66659-2-doug@schmorgal.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| can_kvaser_pci.c | ||
| can_mioe3680_pci.c | ||
| can_pcm3680_pci.c | ||
| can_sja1000.c | ||
| can_sja1000.h | ||
| ctu_can_fd_frame.h | ||
| ctu_can_fd_regs.h | ||
| ctucan_core.c | ||
| ctucan_core.h | ||
| ctucan_pci.c | ||
| meson.build | ||
| trace-events | ||
| trace.h | ||
| xlnx-versal-canfd.c | ||
| xlnx-zynqmp-can.c | ||