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qemu/hw/riscv
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Ivan Klokov 1addf57177 target/riscv: Add RISC-V CSR qtest support 
The RISC-V architecture supports the creation of custom
CSR-mapped devices. It would be convenient to test them in the same way
as MMIO-mapped devices. To do this, a new call has been added
to read/write CSR registers.

Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Acked-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-01-17 11:48:43 -03:00
..
boot.c Accel & Exec patch queue 2024-12-21 11:07:00 -05:00
Kconfig hw/riscv: Add Microblaze V generic board 2024-12-20 11:22:47 +10:00
meson.build hw/riscv: Add Microblaze V generic board 2024-12-20 11:22:47 +10:00
microblaze-v-generic.c Accel & Exec patch queue 2024-12-21 11:07:00 -05:00
microchip_pfsoc.c Accel & Exec patch queue 2024-12-21 11:07:00 -05:00
numa.c include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
opentitan.c Accel & Exec patch queue 2024-12-21 11:07:00 -05:00
riscv-iommu-bits.h hw/riscv/riscv-iommu: parametrize CAP.IGS 2024-12-20 11:19:16 +10:00
riscv-iommu-pci.c RISC-V PR for 10.0 2024-12-21 08:13:16 -05:00
riscv-iommu-sys.c hw/riscv/riscv-iommu-sys.c: fix duplicated 'table_size' 2024-12-28 14:42:53 +03:00
riscv-iommu.c RISC-V PR for 10.0 2024-12-21 08:13:16 -05:00
riscv-iommu.h hw/riscv/riscv-iommu: implement reset protocol 2024-12-20 11:22:46 +10:00
riscv_hart.c target/riscv: Add RISC-V CSR qtest support 2025-01-17 11:48:43 -03:00
shakti_c.c include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
sifive_e.c Accel & Exec patch queue 2024-12-21 11:07:00 -05:00
sifive_u.c Accel & Exec patch queue 2024-12-21 11:07:00 -05:00
spike.c Accel & Exec patch queue 2024-12-21 11:07:00 -05:00
trace-events hw/riscv/riscv-iommu: implement reset protocol 2024-12-20 11:22:46 +10:00
trace.h hw/riscv: add RISC-V IOMMU base emulation 2024-10-31 13:51:24 +10:00
virt-acpi-build.c Accel & Exec patch queue 2024-12-21 11:07:00 -05:00
virt.c hw/pci-host/gpex: Allow more than 4 legacy IRQs 2024-12-30 20:04:50 +01:00