mirror of
https://github.com/Motorhead1991/qemu.git
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1c20d3ff60
Move the binary and device tree loading code to the machine done notifier. This allows us to prepare for editing the device tree as part of the notifier. This is based on similar code in the ARM virt machine. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-2-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
120 lines
3.4 KiB
C
120 lines
3.4 KiB
C
/*
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* QEMU RISC-V VirtIO machine interface
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_VIRT_H
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#define HW_RISCV_VIRT_H
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#include "hw/riscv/riscv_hart.h"
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#include "hw/sysbus.h"
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#include "hw/block/flash.h"
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#include "qom/object.h"
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#define VIRT_CPUS_MAX_BITS 9
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#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
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#define VIRT_SOCKETS_MAX_BITS 2
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#define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS)
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#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
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typedef struct RISCVVirtState RISCVVirtState;
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DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE,
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TYPE_RISCV_VIRT_MACHINE)
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typedef enum RISCVVirtAIAType {
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VIRT_AIA_TYPE_NONE = 0,
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VIRT_AIA_TYPE_APLIC,
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VIRT_AIA_TYPE_APLIC_IMSIC,
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} RISCVVirtAIAType;
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struct RISCVVirtState {
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/*< private >*/
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MachineState parent;
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/*< public >*/
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Notifier machine_done;
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RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
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DeviceState *irqchip[VIRT_SOCKETS_MAX];
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PFlashCFI01 *flash[2];
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FWCfgState *fw_cfg;
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int fdt_size;
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bool have_aclint;
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RISCVVirtAIAType aia_type;
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int aia_guests;
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};
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enum {
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VIRT_DEBUG,
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VIRT_MROM,
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VIRT_TEST,
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VIRT_RTC,
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VIRT_CLINT,
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VIRT_ACLINT_SSWI,
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VIRT_PLIC,
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VIRT_APLIC_M,
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VIRT_APLIC_S,
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VIRT_UART0,
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VIRT_VIRTIO,
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VIRT_FW_CFG,
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VIRT_IMSIC_M,
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VIRT_IMSIC_S,
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VIRT_FLASH,
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VIRT_DRAM,
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VIRT_PCIE_MMIO,
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VIRT_PCIE_PIO,
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VIRT_PCIE_ECAM
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};
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enum {
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UART0_IRQ = 10,
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RTC_IRQ = 11,
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VIRTIO_IRQ = 1, /* 1 to 8 */
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VIRTIO_COUNT = 8,
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PCIE_IRQ = 0x20, /* 32 to 35 */
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VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
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};
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#define VIRT_IRQCHIP_IPI_MSI 1
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#define VIRT_IRQCHIP_NUM_MSIS 255
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#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
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#define VIRT_IRQCHIP_NUM_PRIO_BITS 3
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#define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
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#define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
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#define VIRT_PLIC_PRIORITY_BASE 0x04
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#define VIRT_PLIC_PENDING_BASE 0x1000
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#define VIRT_PLIC_ENABLE_BASE 0x2000
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#define VIRT_PLIC_ENABLE_STRIDE 0x80
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#define VIRT_PLIC_CONTEXT_BASE 0x200000
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#define VIRT_PLIC_CONTEXT_STRIDE 0x1000
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#define VIRT_PLIC_SIZE(__num_context) \
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(VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
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#define FDT_PCI_ADDR_CELLS 3
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#define FDT_PCI_INT_CELLS 1
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#define FDT_PLIC_INT_CELLS 1
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#define FDT_APLIC_INT_CELLS 2
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#define FDT_IMSIC_INT_CELLS 0
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#define FDT_MAX_INT_CELLS 2
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#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
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1 + FDT_MAX_INT_CELLS)
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#define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
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1 + FDT_PLIC_INT_CELLS)
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#define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
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1 + FDT_APLIC_INT_CELLS)
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#endif
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