mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-19 16:12:40 -06:00
38ba38d87d
Introduce a new ast2700 INTCIO class to support AST2700 INTCIO.
Added new register definitions for INTCIO, including enable and status
registers for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTCIO, supporting six input pins and six
output pins, aligning with the newly defined registers.
Implemented "aspeed_intcio_read" and "aspeed_intcio_write" to handle
INTCIO-specific register access.
To GICINT196 |
ETH1 |-----------| |--------------------------|
-------->|0 | | INTCIO |
ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|
-------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|
ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|
-------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|
UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|
-------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|
UART1 | 22| |--------------------------|
-------->|8 23|
UART2 | 24|
-------->|9 25|
UART3 | 26|
---------|10 27|
UART5 | 28|
-------->|11 29|
UART6 | |
-------->|12 30|
UART7 | 31|
-------->|13 |
UART8 | OR[0:31] |
-------->|14 |
UART9 | |
-------->|15 |
UART10 | |
-------->|16 |
UART11 | |
-------->|17 |
UART12 | |
-------->|18 |
|-----------|
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-18-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
62 lines
1.4 KiB
C
62 lines
1.4 KiB
C
/*
|
|
* ASPEED INTC Controller
|
|
*
|
|
* Copyright (C) 2024 ASPEED Technology Inc.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0-or-later
|
|
*/
|
|
#ifndef ASPEED_INTC_H
|
|
#define ASPEED_INTC_H
|
|
|
|
#include "hw/sysbus.h"
|
|
#include "qom/object.h"
|
|
#include "hw/or-irq.h"
|
|
|
|
#define TYPE_ASPEED_INTC "aspeed.intc"
|
|
#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
|
|
#define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
|
|
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
|
|
|
|
#define ASPEED_INTC_MAX_INPINS 10
|
|
#define ASPEED_INTC_MAX_OUTPINS 19
|
|
|
|
typedef struct AspeedINTCIRQ {
|
|
int inpin_idx;
|
|
int outpin_idx;
|
|
int num_outpins;
|
|
uint32_t enable_reg;
|
|
uint32_t status_reg;
|
|
} AspeedINTCIRQ;
|
|
|
|
struct AspeedINTCState {
|
|
/*< private >*/
|
|
SysBusDevice parent_obj;
|
|
|
|
/*< public >*/
|
|
MemoryRegion iomem;
|
|
MemoryRegion iomem_container;
|
|
|
|
uint32_t *regs;
|
|
OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
|
|
qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS];
|
|
|
|
uint32_t enable[ASPEED_INTC_MAX_INPINS];
|
|
uint32_t mask[ASPEED_INTC_MAX_INPINS];
|
|
uint32_t pending[ASPEED_INTC_MAX_INPINS];
|
|
};
|
|
|
|
struct AspeedINTCClass {
|
|
SysBusDeviceClass parent_class;
|
|
|
|
uint32_t num_lines;
|
|
uint32_t num_inpins;
|
|
uint32_t num_outpins;
|
|
uint64_t mem_size;
|
|
uint64_t nr_regs;
|
|
uint64_t reg_offset;
|
|
const MemoryRegionOps *reg_ops;
|
|
const AspeedINTCIRQ *irq_table;
|
|
int irq_table_count;
|
|
};
|
|
|
|
#endif /* ASPEED_INTC_H */
|