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8be545ba5a
Convert the existing includes with sed -i ,exec/memory.h,system/memory.h,g Move the include within cpu-all.h into a !CONFIG_USER_ONLY block. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
105 lines
3.4 KiB
C
105 lines
3.4 KiB
C
/*
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* defines common to all virtual CPUs
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_ALL_H
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#define CPU_ALL_H
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#include "exec/page-protection.h"
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#include "exec/cpu-common.h"
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#include "exec/cpu-interrupt.h"
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#include "exec/tswap.h"
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#include "hw/core/cpu.h"
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#include "exec/cpu-defs.h"
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#include "exec/target_page.h"
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#ifndef CONFIG_USER_ONLY
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#include "system/memory.h"
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#endif
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CPUArchState *cpu_copy(CPUArchState *env);
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#include "cpu.h"
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#ifdef CONFIG_USER_ONLY
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/*
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* Allow some level of source compatibility with softmmu. We do not
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* support any of the more exotic features, so only invalid pages may
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* be signaled by probe_access_flags().
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*/
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#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
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#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2))
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#define TLB_WATCHPOINT 0
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#else
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/*
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* Flags stored in the low bits of the TLB virtual address.
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* These are defined so that fast path ram access is all zeros.
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* The flags all must be between TARGET_PAGE_BITS and
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* maximum address alignment bit.
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*
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* Use TARGET_PAGE_BITS_MIN so that these bits are constant
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* when TARGET_PAGE_BITS_VARY is in effect.
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*
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* The count, if not the placement of these bits is known
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* to tcg/tcg-op-ldst.c, check_max_alignment().
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*/
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/* Zero if TLB entry is valid. */
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#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
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/* Set if TLB entry references a clean RAM page. The iotlb entry will
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contain the page physical address. */
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#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
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/* Set if TLB entry is an IO callback. */
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#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
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/* Set if TLB entry writes ignored. */
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#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4))
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/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
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#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5))
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/*
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* Use this mask to check interception with an alignment mask
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* in a TCG backend.
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*/
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#define TLB_FLAGS_MASK \
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(TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
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| TLB_FORCE_SLOW | TLB_DISCARD_WRITE)
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/*
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* Flags stored in CPUTLBEntryFull.slow_flags[x].
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* TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x].
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*/
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/* Set if TLB entry requires byte swap. */
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#define TLB_BSWAP (1 << 0)
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/* Set if TLB entry contains a watchpoint. */
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#define TLB_WATCHPOINT (1 << 1)
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/* Set if TLB entry requires aligned accesses. */
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#define TLB_CHECK_ALIGNED (1 << 2)
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#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED)
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/* The two sets of flags must not overlap. */
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QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
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#endif /* !CONFIG_USER_ONLY */
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/* Validate correct placement of CPUArchState. */
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QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
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QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
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#endif /* CPU_ALL_H */
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