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The LPC Controller on POWER9 is very similar to the one found on POWER8 but accesses are now done via on MMIOs, without the XSCOM and ECCB logic. The device tree is populated differently so we add a specific POWER9 routine for the purpose. SerIRQ routing is yet to be done. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-7-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
99 lines
2.7 KiB
C
99 lines
2.7 KiB
C
/*
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* QEMU PowerPC PowerNV LPC controller
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*
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* Copyright (c) 2016, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _PPC_PNV_LPC_H
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#define _PPC_PNV_LPC_H
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#include "hw/ppc/pnv_psi.h"
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#define TYPE_PNV_LPC "pnv-lpc"
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#define PNV_LPC(obj) \
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OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC)
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#define TYPE_PNV8_LPC TYPE_PNV_LPC "-POWER8"
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#define PNV8_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV8_LPC)
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#define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9"
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#define PNV9_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV9_LPC)
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typedef struct PnvLpcController {
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DeviceState parent;
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uint64_t eccb_stat_reg;
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uint32_t eccb_data_reg;
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/* OPB bus */
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MemoryRegion opb_mr;
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AddressSpace opb_as;
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/* ISA IO and Memory space */
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MemoryRegion isa_io;
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MemoryRegion isa_mem;
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MemoryRegion isa_fw;
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/* Windows from OPB to ISA (aliases) */
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MemoryRegion opb_isa_io;
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MemoryRegion opb_isa_mem;
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MemoryRegion opb_isa_fw;
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/* Registers */
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MemoryRegion lpc_hc_regs;
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MemoryRegion opb_master_regs;
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/* OPB Master LS registers */
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uint32_t opb_irq_stat;
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uint32_t opb_irq_mask;
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uint32_t opb_irq_pol;
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uint32_t opb_irq_input;
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/* LPC HC registers */
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uint32_t lpc_hc_fw_seg_idsel;
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uint32_t lpc_hc_fw_rd_acc_size;
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uint32_t lpc_hc_irqser_ctrl;
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uint32_t lpc_hc_irqmask;
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uint32_t lpc_hc_irqstat;
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uint32_t lpc_hc_error_addr;
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/* XSCOM registers */
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MemoryRegion xscom_regs;
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/* PSI to generate interrupts */
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PnvPsi *psi;
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} PnvLpcController;
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#define PNV_LPC_CLASS(klass) \
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OBJECT_CLASS_CHECK(PnvLpcClass, (klass), TYPE_PNV_LPC)
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#define PNV_LPC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PnvLpcClass, (obj), TYPE_PNV_LPC)
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typedef struct PnvLpcClass {
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DeviceClass parent_class;
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int psi_irq;
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DeviceRealize parent_realize;
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} PnvLpcClass;
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/*
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* Old compilers error on typdef forward declarations. Keep them happy.
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*/
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struct PnvChip;
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ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
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int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset);
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#endif /* _PPC_PNV_LPC_H */
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