mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 16:23:55 -06:00
143d6785ef
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-5-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
79 lines
3.6 KiB
Text
79 lines
3.6 KiB
Text
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# LoongArch instruction decode definitions.
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#
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# Copyright (c) 2021 Loongson Technology Corporation Limited
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#
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#
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# Fields
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#
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%sa2p1 15:2 !function=plus_1
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#
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# Argument sets
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#
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&r_i rd imm
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&rrr rd rj rk
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&rr_i rd rj imm
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&rrr_sa rd rj rk sa
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#
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# Formats
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#
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@rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr
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@r_i20 .... ... imm:s20 rd:5 &r_i
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@rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i
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@rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i
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@rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i
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@rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1
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#
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# Fixed point arithmetic operation instruction
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#
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add_w 0000 00000001 00000 ..... ..... ..... @rrr
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add_d 0000 00000001 00001 ..... ..... ..... @rrr
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sub_w 0000 00000001 00010 ..... ..... ..... @rrr
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sub_d 0000 00000001 00011 ..... ..... ..... @rrr
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slt 0000 00000001 00100 ..... ..... ..... @rrr
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sltu 0000 00000001 00101 ..... ..... ..... @rrr
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slti 0000 001000 ............ ..... ..... @rr_i12
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sltui 0000 001001 ............ ..... ..... @rr_i12
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nor 0000 00000001 01000 ..... ..... ..... @rrr
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and 0000 00000001 01001 ..... ..... ..... @rrr
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or 0000 00000001 01010 ..... ..... ..... @rrr
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xor 0000 00000001 01011 ..... ..... ..... @rrr
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orn 0000 00000001 01100 ..... ..... ..... @rrr
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andn 0000 00000001 01101 ..... ..... ..... @rrr
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mul_w 0000 00000001 11000 ..... ..... ..... @rrr
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mulh_w 0000 00000001 11001 ..... ..... ..... @rrr
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mulh_wu 0000 00000001 11010 ..... ..... ..... @rrr
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mul_d 0000 00000001 11011 ..... ..... ..... @rrr
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mulh_d 0000 00000001 11100 ..... ..... ..... @rrr
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mulh_du 0000 00000001 11101 ..... ..... ..... @rrr
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mulw_d_w 0000 00000001 11110 ..... ..... ..... @rrr
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mulw_d_wu 0000 00000001 11111 ..... ..... ..... @rrr
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div_w 0000 00000010 00000 ..... ..... ..... @rrr
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mod_w 0000 00000010 00001 ..... ..... ..... @rrr
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div_wu 0000 00000010 00010 ..... ..... ..... @rrr
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mod_wu 0000 00000010 00011 ..... ..... ..... @rrr
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div_d 0000 00000010 00100 ..... ..... ..... @rrr
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mod_d 0000 00000010 00101 ..... ..... ..... @rrr
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div_du 0000 00000010 00110 ..... ..... ..... @rrr
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mod_du 0000 00000010 00111 ..... ..... ..... @rrr
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alsl_w 0000 00000000 010 .. ..... ..... ..... @rrr_sa2p1
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alsl_wu 0000 00000000 011 .. ..... ..... ..... @rrr_sa2p1
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alsl_d 0000 00000010 110 .. ..... ..... ..... @rrr_sa2p1
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lu12i_w 0001 010 .................... ..... @r_i20
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lu32i_d 0001 011 .................... ..... @r_i20
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lu52i_d 0000 001100 ............ ..... ..... @rr_i12
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pcaddi 0001 100 .................... ..... @r_i20
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pcalau12i 0001 101 .................... ..... @r_i20
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pcaddu12i 0001 110 .................... ..... @r_i20
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pcaddu18i 0001 111 .................... ..... @r_i20
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addi_w 0000 001010 ............ ..... ..... @rr_i12
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addi_d 0000 001011 ............ ..... ..... @rr_i12
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addu16i_d 0001 00 ................ ..... ..... @rr_i16
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andi 0000 001101 ............ ..... ..... @rr_ui12
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ori 0000 001110 ............ ..... ..... @rr_ui12
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xori 0000 001111 ............ ..... ..... @rr_ui12
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