Alistair Francis d4452c6924 hw/riscv: virt: Allow support for 32 cores ... Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so let's set that as the maximum for the virt board. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/435 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220105213937.1113508-9-alistair.francis@opensource.wdc.com>		2022-01-08 15:46:09 +10:00
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boot.h	hw/riscv: boot: Add a PLIC config string function	2021-10-28 14:39:23 +10:00
boot_opensbi.h	riscv: Add opensbi firmware dynamic support	2020-07-13 17:25:37 -07:00
microchip_pfsoc.h	hw/riscv: microchip_pfsoc: Use the PLIC config helper function	2021-10-28 14:39:23 +10:00
numa.h	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.h	hw/riscv: opentitan: Update to the latest build	2021-10-22 23:35:47 +10:00
riscv_hart.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
shakti_c.h	hw/riscv: Connect Shakti UART to Shakti platform	2021-05-11 20:02:06 +10:00
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e.h	sifive_e: Rename memmap enum constants	2020-09-18 13:49:48 -04:00
sifive_u.h	hw/riscv: sifive_u: Use the PLIC config helper function	2021-10-28 14:39:23 +10:00
spike.h	riscv: spike: Remove target macro conditionals	2020-12-17 21:56:44 -08:00
virt.h	hw/riscv: virt: Allow support for 32 cores	2022-01-08 15:46:09 +10:00